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OCTOBER 2026 I I-CONNECT007 MAGAZINE 37 B E YO N D D ES I G N Two simple geometric truths govern SI: 1. Traces close together increase mutual induc- tance, meaning more crosstalk. Two individual traces should be kept well apart to reduce crosstalk. 2. Traces tightly coupled to their reference plane reduce loop inductance, meaning cleaner sig- nals. A signal trace should be tightly coupled to its return path (plane) to increase coupling and reduce inductance. The PDN'S High-frequency Ceiling A PDN is far more than a set of power traces and scattered capacitors; it behaves as a distributed AC-impedance system that must simultaneously deliver high transient current with minimal voltage noise, maintain impedance below the target level across nine decades of frequency, provide a clean and continuous return path for high-speed signals, and suppress cavity resonance, ground bounce, and EMI radiation. In the time domain, a decoupling capacitor acts as a local energy reservoir, supplying instantaneous current to the processor during fast load transients until the voltage regulator can respond. However, in the frequency domain, that same capacitor reduces the PDN's AC impedance around its self-resonant frequency, enabling more high-frequency current to reach the IC with minimal voltage noise. By lowering impedance and providing instanta- neous charge, decoupling capacitors suppress dI/ dt noise, simultaneous switching noise (SSN), rail collapse during burst activity, and jitter induced by supply modulation. Plus, a decoupling capac- itor provides a local displacement-current loop between power and ground, reducing loop induc- tance, switching noise, common-mode radiation, and ground bounce. As operating frequencies and rise times increase, the PDN's AC impedance climbs because the induc- tance of the bypass and decoupling capacitors becomes the limiting factor. Every capacitor includes an equivalent series inductance (ESL) component, which causes its impedance to rise at high frequen- cies. Bulk capacitors work well up to roughly 10 MHz, and ceramic capacitors extend coverage into the hundreds of megahertz. Above that, only the PCB's plane capacitance and on-die capacitors can mean- ingfully suppress PDN impedance. A single capacitor covers only a narrow band. A network of capacitors—bulk, mid-frequency, high- frequency—creates a stair-step impedance profile that keeps PDN impedance below target from kHz to hundreds of MHz. This is why "one capac- itor per pin" is a myth. You need a distribution of values and ESLs. However, the power/ground plane pair acts almost like a perfect capacitor, with negli- gible inductance (no leads) and very low equiva- lent series resistance (ESR), making it ideal for ultra high-frequency noise suppression. Tight plane spacing (<5 mil) further boosts this high-frequency capacitance that lowers PDN impedance, reduces switching noise, supports fast transient currents, and improves overall PI stability. Figure 2 illustrates the relationship between capacitance, resistance, and inductance of a capac- itor. If the capacitance is increased, then so is the frequency response. However, it is inevitably the mounting and spreading inductance that pushes the response down. There is, however, a leverage point that designers can use to minimize mounting inductance. The loop area formed by the capacitor, its vias, and the planes determines mounting inductance. Reduce the loop area, and PI improves dramatically. So, we need to place the vias closer to the component lands. The best practice hierarchy for via fanout: 1. Via in pad (lowest inductance) 2. Dual vias adjacent to pad 3. Single via close to pad 4. End via fanout (worst case) Never use thermal reliefs on PDN vias; they add inductance and sabotage high frequency performance. Return Path Discontinuities (RPDs): The Hidden SI Killer Designers obsess over trace length but often ignore the return path. If the return displacement current must detour around a void, split, or poorly placed