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characteristics of epig deposits for fine-line applications continues Figure 20: Wide scan results by AES; EPIG (Pd 0.1 µm, Au 0.1 µm) as plated, after heat treatment, after heat treatment and plasma treatment. of 20 nm point from Au surface. It was considered that the diffusion of Pd was not dependent on Pd thickness, and was greatly dependent on Au thickness. The thicker Au layer will be important for keeping lower ratio of Pd in Au layer. This ratio of Pd in the Au layer was related to WBR after heat treatment. From this study, when using the condition of heat treatment for 16 hours at 175°C used, Pd thickness at least 0.15 µm and Au thickness of 0.20 µm will be needed. Plasma Treatment for Wire Bonding The effect of plasma treatment for EPIG film after heat treatment was confirmed as shown in Figure 19 and Figure 20 with Ar being used for the plasma gas. After plasma treatment, the strength of wire pull test and the broken mode became better, compared with that of the sample with heat treatment. It was confirmed by AES analysis that the peak of Cu was removed by the plasma treatment. Conclusion EPIG process had better pattern ability for narrow lines and spaces, compared with the ENEPIG process. When using LF35 as the solder ball for EPIG deposits, thin and uniform IMC layers were 28 The PCB Magazine • January 2014 formed. As a result, SJR became better. When Au and Pd thickness was thinner, EPIG film had poorer WBR after heat treatment because Cu diffused onto the Au surface and the ratio of Pd in Au layer was higher. If using suitable Pd and Au thickness for EPIG, its WBR became better. In addition, it was suggested that WBR could be improved by plasma treatment to Au surface after heat exposure. PCB References 1. Katsuhisa Tanabe, Masayuki Kiso, Kota Kitajima, Tatsushi Someya, C. Uyemura & Corporation Co., Ltd., Central Research Laboratory, Osaka, Japan, and Don Gudeczauskas and George Milad, UIC Technical Center, Southington, CT, USA. 2. Chi-Won Hwang, Katusaki Suganµma. J. Mater. Res., 18, 2540, Nov (2003). 3. Donald Gudeczauskas et al, 39th International Symposium on Microelectronics, October 8–12, 2006, San Diego. 4. V. Vuorinen, T Laurila, H. Yu, and J. K. Kivilahti. J. appl. Phys. 99, 023530 (2006). 5. Yukinori Oda, Masayuki Kiso, Akira Okada, Kota Kitajima, Shigeo Hashimoto, George Milad, Don Gudeczauskas, 41st International Symposiµm on Microelectronics, Providence, RI, Nov (2008).