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beyond design pdn planning and capacitor selection, part 2 continues reflecting at the ends creating resonances in the pling capacitors have little effect over 1GHz and transmission line. As the frequency increases the only way to reduce the AC impedance of the to half wavelength, the series resonance builds PDN above this frequency is to use ECM or alternatively on-die capacitance. These ultra-thin up a standing wave pattern reflecting from the laminates replace the conventional power and open edges of the plane. Fortunately, this happens above 1GHz. ground planes and have excellent stability of dielectric constant and loss up to 15GHz. Also, the mounting inductance of each capacitor needs to be taken into account. The In Figure 6, the ICD PDN Planner shows mounting inductance is comprised of three the one value per decade approach including components: Capacitor footprint and fanout, the voltage regulator module (VRM) which is capacitor height above or below the plane and mainly inductive, the total loop inductance of power plane spreading inductance. These three each capacitor, via spreading inductance and elements describe the loop in which current the plane capacitance. The plane resonance can must flow—the bigger the loop, the more the inbe seen on the right. In each case, a 0.24mil, 3M ductance. The footprint (land pattern) for a caECM, that provides 20nF/in2, was used to drop pacitor dominates the total ESL. It consists of via the PDN to below the simulated target impedance up to 1.3GHz. By comparison, placement with respect to the pad, the target frequency and the optithe length and width of traces mized value approached in Figconnected to the pad, and the This technology ure 7, also have the VRM, loop way the vias are connected to inductance and plane capacithe power and ground planes. provides an effective tance of 3M ECM included. The location of the power/ approach for decoupling ground planes in the PCB So which approach is best? stackup controls the height high-performance ICs 1. The target frequency apof the via. Inductance directly whilst also reducing proach gives a clean "V" shape depends on the magnetic field, with just one small anti-resoso reducing the energy associelectromagnetic ated with the loop area reducnant peak at 40MHz and is beinterference. es overall inductance. low the target impedance up to The inductance associated 1.3GHz; with current spreading, into the 2. The one value capacitor per power/ground planes, also contribdecade approach has one peak at utes to the total mounted inductance. Current in 23MHz and is also below the target impedance the planes becomes concentrated in the vicinity up to 1.3GHz; and of the vias. This current creates a high magnetic 3. The optimized value approach is also good field and therefore contributes to inductance. from 2.3MHz to 1.3GHz with a peak at 1MHz. With the continuous trend to smaller feature sizes and faster signal rise times, planar caBut, in reality, only plane capacitance, onpacitor laminate or embedded capacitor materidie capacitance or changing the plane size als (ECM) is becoming a cost-effective solution (area) can reduce the impedance beyond several for improved power integrity. This technology 100MHz. provides an effective approach for decoupling So, it is really six of one and half a dozen high-performance ICs whilst also reducing elecof the other! Personally, I prefer the target fretromagnetic interference. quency approach, as it is less time-consuming Planar capacitor technology allows for a very to analyze and requires fewer parts; this means thin dielectric layer (0.24 – 2.0mil) that provides that the BOM count is reduced, holding stock distributive decoupling capacitance, of 20nF/in2 is reduced and assembly equipment setup and in this case. This also increases real estate (space), placement times are greatly reduced. This all reduces the number of vias and opens up routleads to reduction in cost and time to market ing channels. Unfortunately, standard decouand of course a more reliable end product. Also, " " January 2014 • The PCB Design Magazine 37