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34 The PCB Design Magazine • February 2014 stitching vias may help alleviate this problem. We've covered differential clock and strobe routing in previous columns, but let's look at address routing. Fly-by topology—as used in double data rate design—uses a daisy-chain or multi-drop topology on address, command and control signals. Fly-by topology reduces simultaneous switch- ing noise (SSN) by deliberately causing flight-time skew between the data and strobes at every chip/ SDRAM requiring controllers to compensate for this skew by adjusting the timing per byte lane. In this case, a series terminator (R11) is em- ployed close to the driver and a parallel 100 ohm VTT pull-up (R18 resistor network) at the end of the loads. If the distance from the source to the first load is short, then the series termina- tor may not be required. But, this should be de- termined by simulation. The ideal location for end terminators is past the last load—with no side branch or stub—as depicted. Stub length should be kept to a minimum. You can see how the address line, highlighted in Figure 6, is routed directly over the memo- ry/load pin with a very short stub going off to each load. Since this stub is extremely short, compared to the transmission line length and length of the rising edge, an impedance mis- match is avoided. Short stubs, and their associ- ated receiver capacitance, act like simple capaci- tive loads which tend to roll-off the rising edge. This configuration is ideal for DDR design but what if there is a slower rise-time clock that needs to be distributed to a number of loads? Star routing is ideal for distributing clocks to multiple loads and is also used for power distribution on signal layers. The routing fans- out from a central point and connects to each load. But, with distributed loads also comes un- matched lengths between the loads. If a single series terminator is used, close to the source as in Figure 7, the different trace lengths cause dif- ferent delays to each load which is unavoidable unless the lengths are matched. This also cre- ates reflections which can be seen in Figure 8. Reflections occur whenever the impedance of the transmission line changes along its length. This can be caused by unmatched drivers/loads, layer transitions, different dielectric materi- als, stubs, vias, connectors and IC packages. By understanding the causes of these reflections and eliminating the source of the mismatch, a design can be engineered with reliable perfor- mance. In Figure 9, three individual series termina- tors are used in conjunction with three different trace lengths. Figure 10 illustrates the resultant clean waveform. If all the trace lengths, of the star configu- ration, are matched to length/delay then these reflections do not occur. So there is a choice: match the lengths or use individual series ter- beyond design EFFECTIVE RoUTING oF MULTIPLE LoADS continues Figure 6: Multi-drop address routing.