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42 The PCB Design Magazine • March 2014 article Properly Designing PCB Footprints by Nicholaus Smith inTeGrATeD DeviCe TeChnoloGY inC. Today the geometries of board-level circuits are being driven to optimize space, cost, and performance, resulting in a large selection of fine-pitch components, connectors, and inte- grated circuits. Overcoming the challenges and the complexities of the circuit is challenging enough without considering the obstacles of mass producing the end-product with extreme- ly high yield expectations. Improperly defined PCB footprints are the culprits behind thousands of costly, time-con- suming failure analysis investigations. For the sake of simplicity, it will be assumed that the circuit and all connections are schematically correct and any failures are the result of unreli- able footprint designs assembled properly onto the PCB. The most common failures are caused by solder shorts or open circuits that develop during assembly. Other potential defects in- clude poorly contemplated pin escape routing, improper thermal design, and the dreaded in- termittent failure. It is imperative to implement PCB layouts with a strong understanding of the assembly process and how the PCB component footprint can influence yield and performance. This is es- pecially important today, due to factors such as: (a) the expansion of integrated circuit product lines manufactured with pin pitches specified at 0.4 mm and below, and (b) the plethora of package variations available, such as chip scale packages (CSP) and quad flat packages (QFN) in double and single rows. Prior to addressing footprint design tech- niques, we must define some layer definitions used in PCB manufacturing, and explain how these layers impact the final board. The pin will be identified as the actual solder contact point