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April 2014 • The PCB Magazine 19 LEAD-FREE REFLOW FOR HIGH-LAYER-COUNT PCBS continues The Role of Reliable Blind Vias At the end of the day, one must develop core competencies at the fabrication side of the supply chain, for the process chemistry side. Keeping in mind one is ultimately working to build long-term reliability in the printed wiring board. While many of those competencies have been discussed in this paper, it would be wise to expound on the critical success factors and pro- cess competencies required to build reliaibility into the microvia. Key Processes Several processes must be implemented in order to ensure success with blind vias and the overall goal of reducing the number of layers in the package. These are: • Desmear • Metalization • Electrodeposition and via filling • Half-etching process This issue becomes increasingly complicated as HDI migrates into designs containing both through-holes and blind vias. Desmear Consider the need to ensure a clean and ac- tive capture pad and its importance on via reli- ability. Any residue remains on the capture pad will at the very least impact plating adhesion (Figure 6). The residues could be from incomplete abla- tion with the laser or inadequate performance from the desmear chemistry (either alkaline permanganate or plasma). It is wise to ensure that the alkaline permanganate (if used) must be optimzed for the type of resin in the particu- lar HDI build-up. Care must be talken to avoid aggressive attack of the resin at the interface of the via wall and capture pad. When processing resin materials that formu- lated for lead-free assembly, the engineer must be cognizant of the fact that these Pb-free de- signed resins are more resistant to alkaline per- manganate chemistry than the lower Tg resins. It would be wise to consider alternative desmear protocols such as combinations of plasma desmear and alkaline permanganate. A second options is to use newer generation solvent swell chemistry, which is better designed to effect penetration into the resin-poly mer matrix. Figure 5: total insertion loss from backplane-daughter cards' architecture from various contributors like traces, connector and vias [6] .