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42 The PCB Design Magazine • June 2014 • ENIG can be applied as a full body finish, or the more common (and recommended) way as a selective finish, because it is applied after solder mask. • The plating of fine patterns (15 µm spac- ing) clearly favors palladium/gold (Pd/Au) or EPIG. • Solder mask over bare copper (SMOBC) processing is best for high-speed design. • There are four design concerns associated with ENIG plating: solder mask defined BGA pads, single sided plugged vias, solder mask bridges and the impact on the conductor's loss characteristics at high frequencies. • Selection of low-loss plating is just as criti- cal as the selection of dielectric material when designing high-frequency circuits. • The resonant behavior of the nickel com- ponent in ENIG increases insertion loss at 2.7 GHz. Avoid using full body ENIG coating of microstrip traces at high frequencies—SMOBC processing should be considered for all high- speed designs. PCBDESIgN References 1. Barry Olney: Beyond Design: Ground Pours, Beyond Design: Electromagnetic Fields, Part 1, Beyond Design: Electromagnetic Fields, Part 2, Beyond Design: Mythbusting - There are no One-way Trips! 2. IPC-4552 – Specification for ENIG Plating for Printed Circuit Boards 3. Henry Ott: Electromagnetic Compatibil- ity Engineering 4. Howard Johnson: High-Speed Signal Propagation 5. John Coonrod, Rogers Corporation: "Un- derstanding PCBs for High-Frequency Applica- tions," Printed Circuit Design & Fabrication 6. Yuriy Shlepnev, Simberian Electromag- netic Solutions, Simbeor Application Notes 7. Dr. Al Horn, Rogers Corporation, "In- creased Circuit Loss due to Ni/Au" The ICD Stackup Planner and PDN Planner can be downloaded from SURFACE FINISHES FoR HIgH-SPEED PCBS continues beyond design Barry olney is managing director of in-Circuit Design Pty ltd (iCD), australia. This PCB design service bureau specializes in board-level simulation, and has developed the iCD Stackup Planner and iCD PDn Planner software. To read past columns, or to contact olney, click here. 2D Transistor Paves Way to Faster electronics Faster electronic device architectures are in the offing with the unveiling of the world's first fully two-dimensional field-effect transistor (FeT) by researchers with lawrence Berkeley national laboratory (Berkeley lab). unlike conventional FeTs made from silicon, these 2D FeTs suffer no performance drop-off under high voltages and provide high electron mobility, even when scaled to a monolayer in thickness. ali Javey, a faculty scientist in Berkeley lab's Materials Sciences Division and a uC Berkeley professor of electrical engineering and computer science, led this research in which 2D hetero - structures were fabricated from layers of a tran- sition metal dichalcogenide, hexagonal boron nitride and graphene stacked via van der Waals interactions. "in constructing our 2D FeTs so that each com- ponent is made from layered materials with van der Waals interfaces, we provide a unique device structure in which the thickness of each compo- nent is well-defined without any surface rough- ness, not even at the atomic level," Javey says. For the 2D FeTs produced in this study, me- chanical exfoliation was used to create the lay- ered components. in the future, Javey and his team will look into growing these heterogeneous layers directly on a substrate. They will also look to scale down the thickness of individual compo- nents to a monolayer. 2D Transistor Paves Way to Faster Electronics

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