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44 The PCB Design Magazine • June 2014 article groups. During DDR3 layout, the interface is split into the command group, the control group, the address group, as well as data banks 0/1/2/3/4/5/6/7, clocks, and others. It's recom- mended that all the signals belonging to the same group be routed "the same way," i.e., us- ing the same topology and layer transitions. As an example, consider the routing se- quence shown in Figure 1. All the DATA 6 group signals go from layer 1 to layer 10, then to lay- er 11, and after that to layer 12. Every signal within the group makes the same layer transi- DDR3 memory is so pervasive, it's almost in- evitable that professional PCB designers will use it. This article advises how to properly fanout and route DDR3 interfaces, even in very high- density and tightly packed board designs. DDR3 Design Rules and Signal groups Everything starts with the recommended high-speed design rules for routing DDR3 in by Robert Feranec FeDevel Routing DDR3 Memory and CPU Fanout Figure 1: all signals in the DaTa 6 group are routed "the same way," using the same topology and layer transitions.

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