Issue link: https://iconnect007.uberflip.com/i/414663
30 The PCB Design Magazine • November 2014 exceptions for some high-end processor chips and FPGAs with hundreds to thousands of I/O.) In addition to these fundamental challeng- es, when die shrink is carried out with next- generation die (most often to improve silicon use efficiency), the pad locations nearly always change. Thus any time there is a die shrink, a redesign of the substrate to which it is attached must be done (except in the case of most wire bonded chips). In contrast, the use of fully test- ed and burned in components with established termination locations and lead pitch, allows the fundamental component pad out and and PCB design made with it to be reused even if die shrink has occurred. This is not an insignificant point for consideration. One last point that deceives some in terms of finding our way to a simpler future requires an appreciation of the potential to, at some point in the years ahead, design circuits using basic functional IP blocks rather than purchasing a die of multiple IP blocks integrated into a sin- gle chip, which is representative of a significant number of IC chips. This has been suggested by researchers at the University of Washington and the University of Michigan. In the current para- digm, both the designer and the manufacture must provide for every termination of the die, whether the terminations are of use in the final design or not. That means that there is a multi- plication of opportunity for defects when there could eventually be a reduction. The potential benefits are far-reaching, in that designers could build a new product with only the specific functions they want in their design. The design using functional block only would be smaller and better performing. It would also be cheaper and more reliable, po- tentially much more reliable. One reason for reliability increase is that the IC could possibly be built with an earlier node of IC technology which is intrinsically more reliable due to lon- ger diffusion paths on the chip. An added ben- efit is that it can be done at higher yield. Figure 2 illustrates this concept. This solution is relatively simple and the benefits are many, but the challenge will be to get the industry to rethink its approach to in- COMPONENT SELECTION FOR EASIER DESIGN & MANuFACTuRE OF ELECTRONICS continues article Figure 2: a "disintegrated" circuit comprised of "brick and mortar," in the words of the developers, is essentially a 2.5D interconnection solution which offers unique potential to create asiC-level perfor- mance in a rapid manner by interconnecting functional circuit blocks on an interconnection base which can then be packaged for use at the next level, as suggested by researchers at the university of Wash- ington and the university of Michigan.