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December 2014 • The PCB Design Magazine 41 PCBS FOR MEDICAL APPLICATIONS—A DESIGNER'S PERSPECTIVE continues to stitch the pour to the ground plane all along the controlled impedance traces. These calcula- tions can then be compared with the controlled impedance results from the PCB manufacturer. Unfortunately, the industry standard for PCB manufacturing files is still the old Gerber format. These files never contain quite enough information to be sure the boards will turn out right. They don't contain units, the decimal place can be ambiguous and even the origin is uncertain. It is good practice to disable zero suppression, and use an absolute origin for both Gerbers and drill files. It is also good practice to inspect all files with Gerber viewing software other than the EDA package that generated them. More and more PCB manufacturers now have automated workflows with little human intervention or interaction. Layer misalign- ment or scaling issues can sneak right through the manufacturing process and only be found when the boards are done. Strategies for Planes and Pours It is a good strategy to flood planes rather than using single net planes. This provides the benefit of allowing the odd trace to route on that layer in a pinch. It also makes it easier to segregate power rails, separate planes and avoid interference with impedance controlled traces. Although it made sense in the days of limited file sizes and taped layouts to route planes as negatives, now this just seems like a source of errors either in review or manufacture. Due to modern boards having many volt- age rails, it is rarely advantageous or even pos- sible to use complete power planes other than for ground. Instead, one or a few layers can be dedicated to power routing using fills and fat traces. As a bonus, signals can be snuck through on these layers as well. When pulling power off onto the component layers, it should first hit one or more bypass capacitors with the other pin drilled to ground, then the destination component pin. Ensure flooded regions are stitched well to others. This is especially important on a two layer board where planes are impossible and ground is really just a collection of pours and is quite broken up. Pours should be kept away from controlled impedance traces unless they are part of the controlled impedance strategy. If they are, then they should be well bypassed to ground. Note that impedance controlled traces crossing over fill boundaries will experi- ence impedance discontinuities. These bound- aries should be stitched either with vias to other layers or with bypass caps across the gap. This stitching should occur as close to the traces as possible. It is often problematic to break planes into regions like analog signal ground or power ground. Having one good plane that is well de- coupled to the chassis can be better than break- ing planes up into different power regions. The effects and locations of high frequency switch- ing currents should be carefully considered and controlled. If possible, keep them off the plane. If a plane must be broken into different regions, a line of no-fit caps should be added, just in case. Consideration should be given to the cur- rents of various sub-circuits that will flow through the plane and their impact on other subcircuits along the way. A slight void or cut in the plane to explicitly corral these currents can be an effective strategy to control them. Some- times a different arrangement of sub-circuits will give even better results. Layout EMC Considerations Given that medical devices are heavily regu- lated, at some point electromagnetic compat- ibility will have to be considered. Add ESD & EMC reduction components like TVS diodes and ferrites, even if the board is a prototype with no plans for EMC testing. This provides a head start to flush out problems early. It also plans ahead for a prototype being used beyond what was initially imagined or intended. Con- sider designing in the parts without populating them right away. Then they can be easily added later without cutting and gluing. Consider where noise may come from both on and off of the PCB. Reducing noise at the source is always a better strategy than combat- ting it only where it is creating trouble. An ex- ample of this is the high speed parallel lines to a TFT display. A tidy bank of ferrites right at the driver outputs is often all it needs. This is easiest done at the PCB design stage. article