Issue link: https://iconnect007.uberflip.com/i/446087
52 The PCB Design Magazine • January 2015 Footprint Development: The Foundation of PCB Design Needless to say, every project starts with a schematic, a mechanical description of the board, a stackup, and a complete bill of mate- rials, or BOM. The bedrock of PCB design, the foundation, is footprint development, Albers advises. He refers to the data sheet for virtual- ly every part on every BOM to leave no doubt about exact package descriptions and create proper footprints. In fact, footprint development is the most time-consuming as- pect of nearly every project. "As a rule, the spacing I use between parts is very large," Al- bers points out. "When I build a footprint, I make a reference line for the maximum size of the part, extend outside that by 15 mils for the silkscreen, then 5 mils more for an assem- bly line, and then a minimum of 15 mils beyond that for a package keep-out. That's 35 mils between the body of one part to the edge of the next part footprint, which has the same 35-mil spacing, so that's 70 mils in total from the body of one part to another." "Discretes ordinarily are less than that," he continued. "For a connector that I know you have to get your fingers around, I may enlarge the keep- out boundary by 40 mils. If it's a right-angle connector, the keep-out accounts for clearance needed for the cable at the edge of the board, and so forth: Each part has its own keep-out value. Keeping the boundaries large certainly helps via placement, eases rout- ing, and is better for the silkscreen, but it leaves enough latitude for me to violate the rule when necessary without jeopardizing assembly, if I need to place two parts 10 mils closer." Via size, spacing, and location are the most challenging tasks in design, not routing or part placement. Through-hole vias impact where you can put parts on the opposite side of the board; of course, that's a principal advantage of using blind and buried vias. There's a point at which an HDI approach becomes unavoidable (generally the result of tight BGA pitch) or more economical in terms of yielding more boards per panel to counteract the increased process- ing cost for multiple laminations. A board de- signer who understands fabrication can make a reasoned analysis. Fab Complexity vs. Yield The balance between fabri- cation complexity and yield per panel is not the only economic concern. Sometimes PCB de- signers need to push back, forcefully, against decisions by their engineering depart- ment or procurement. Albers recalls working at a computer company and encountering a BOM that called for a large through-hole capacitor for which there was a surface- mount substitute that would consume much less territory. The capacitor in the call-out cost $0.17 and the substitute cost $2.40 each. Procurement was adamant his group had to use the $0.17 capacitor, not the substitute. So much room was required for the part that just one board would fit on a panel, instead of two if the substitute had been acceptable. It cost the company $7.40 more per board to use the cheaper part instead of the substitute. If a board will be used merely on a benchtop as a test or development tool and only four or five are needed, then the size is irrelevant for manufacture, provided it fits on a panel, cou- pon width included. A design that will be pro- duced in any quantity, however, had better take into account how it can be replicated per panel with minimum waste. If you contemplate using large panels for economy, you need to consider minimum hole and pad sizes because the tol- erance across the panel may not support using 6-mil drills and small annular rings, for exam- TIPS EvERY DESIgNER SHOuLD KNOW continues design for manufacturing If a board will be used merely on a benchtop as a test or development tool and only four or five are needed, then the size is irrelevant for manufacture, provided it fits on a panel, coupon width included. a design that will be produced in any quantity, however, had better take into account how it can be replicated per panel with minimum waste. " "