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36 The PCB Design Magazine • February 2015 this creates the LW 2 upper limit for the volume. To increase capacitance, either the e r relative dielectric constant has to increase, or the th d and/or th c thickness values have to decrease. In case the conductor thickness is much less than the dielectric thickness, the capacitance grows with the inverse square of the dielectric thick- ness. This gives a convenient scaling possibility to improve the volumetric density of ceramic capacitors: if we use thinner dielectric layers, in the given case size we can produce more and more capacitance. However, as we make each dielectric layer thinner, the E field strength from the same V voltage applied across the part grows propor- tionally: Also, if we increase the e r dielectric constant, the D electric displacement field will grow pro- portionally: If we plot the relationship between E and D in high dielectric constant ferroelectric materi- als (Figure 2), D will not follow it proportionally and eventually the curve flattens out, which is called saturation. Over the many years as we, the users, kept asking for more capacitance in the same pack- age, this scaling helped the industry to give us what we asked for. But we get not only more ca- pacitance; we also get more bias sensitivity. To- day the detailed data sheets from major MLCC vendors give us the typical bias sensitivity we can expect from MLCC parts, but unfortunately this kind of data is not a guaranteed specifica- tion. In case we want to collect our own data, the techniques and instrumentation is available in professional form [4] . When we look at the data sheet values or at our own measured data [5] , we can see in some applications we can eas- ily lose up to 80% of the capacitance just to DC bias effects. We can also use simple homemade equip- ment to measure complex reflections and com- plex impedance and from that we can back-cal- culate capacitance. Figure 3 shows the DC bias effect measured with a homemade vector-net- work analyzer on a 100 uF MLCC. The 3D surface is put together from multiple individual frequency sweeps, each with a differ- ent DC bias value across the capacitor. The DC bias voltage is shown on the left axis; the right axis shows frequency. Note that the capacitance depends not only on the bias voltage, but also on frequency. None of these dependencies are present in Class 1 ceramic capacitors. Figure 4 shows the bias-dependence surface for a 0.1 uF COG MLCC. The 3D surface of Figure 4 is flat in both directions until we start approaching the se- ries resonance frequency of the part. There is an increasing noise on the measured surface at very low frequencies. At 100 Hz the imped- ance magnitude of a 0.1 uF capacitor is more than 10 kOhm. The noise illustrates the limi- tation of the simple home-made instrumenta- tion when we try to measure kilo-ohm imped- ance values in two-port shunt-through con- nection. So, be careful when you use a 6.3-rated Class 2 ceramic capacitor in a 5V application: a big percentage of the capacitance may be gone. The good news is that this bias dependence is hardly present in tantalum and aluminum capacitors, film capacitors and printed-circuit laminates. PCBDESIgn EFFECTS OF DC BIAS On CERAMIC CAPACITORS continues quiet power Figure 2: relationship between the e and D fields in ferroelectric materials.