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March 2015 • The PCB Design Magazine 53 We've got this advanced analysis technology tightly integrated with the implementation en- vironment because what will typically happen is you'll run an analysis and it doesn't work— it failed the JEDEC requirements. So, what do I have to do? I have to start working with my power plane, working with the signaling, clean- ing up everything, maybe there are too many vias on the signal, etc. But once you do all this you rerun the analysis and see that you're get- ting closer and you start to see yourself improv- ing. Because it's so tightly integrated, our cus- tomers can accelerate the process of finding the problem, fixing the problem and verifying you fixed the problem. It's been an exciting ride the last two and half years with Sigrity and Cadence, and the Sigrity 2015 release coming out during DesignCon is really the culmination of bringing the latest and greatest technology to the mar- ket and has addressed these very difficult design and analysis challenges around LPDDR4. KD: We have engineers and layout people— people that specifically do SI work. Are these tools used in a team application? BG: The challenge has been that historically, data has just been thrown over the wall: I'm the designer and I throw it over the wall; the SI guy says "fix this" and throws it back over the wall, and it's a typical back-and-forth. It's very diffi- cult to converge. On the other hand, the work that the signal integrity and power integrity en- gineer performs comes from a level of expertise in his area that you can't really expect a PCB designer to have. On the other hand, the person doing integrity analysis doesn't really have the level of expertise to make the changes to the physical design that the PCB designer has. We recognize that, yet we try to provide an envi- ronment which allows the gap to be bridged as much as possible. So our Allegro PCB analysis tools, as I mentioned, have the signal integrity tools residing right on top, so we have an en- vironment where the layout person with some level of knowledge—maybe he knows how to get IBIS model on the web and can attach that to one of his components and can make sure that all of his resistors and capacitors have prop- er values associated with the design database— can actually say let me analyze the signal and see what it looks like. He may not have the ex- pertise to know exactly how to fix it, but at least he can identify there's a problem and then just needs to determine how to resolve it. Our approach here is that we try to let the layout person with some level of electrical background go as far as he can and then bring the expert into the same envi- ronment. It's how we've sort of structured our technology—we've got the base signal integri- ty technology that probably both expert and non-expert can use, and then we have advanced analysis technology that sits on top of that. The expert can go in and run the DDR simultane- ous switching noise analysis. It can figure out that he's going to have 64 bits simultaneously switching and the signal is not going to work. He'll have to make some changes to the power plane to make sure it's more stable, perhaps by adding some more decoupling. He could actual- ly with some level of expertise or knowledge of how to place things around the board put down his own capacitors, try out how it'll work and improve the overall process. KD: Is what you're describing a radical change to front-end design with these new speeds, where it's not your classic front-end de- sign anymore with a simple schematic passed down to a layout designer? BG: It's an excellent question because for quite a long time Cadence has pushed what we've called a constraint-driven flow, where you do a lot of analysis upfront, create constraints, drive those constraints into design and push that forward to layout and verify it at the end. That's basically our methodology that Cadence has put in place for signal integrity, but one of the things we're showing in our booth is that we're moving this constraint-driven flow so it's not just signal integrity, but also power integri- ty. Because we believe that if the hardware en- gineer that is doing the schematic knows this article CADEnCE'S BRAD GRIFFIn DIGS DEEP InTO DDR continues