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April 2015 • The PCB Design Magazine 55 Experiment 1: PCB Area Larger than Required Effective Area. This first experiment will outline a situation where the available power plane area is larger than the effective radius calculated in Equation 2. Shown in Figure 1 is the stack-up used for this experiment. It is an eight-layer board with a top/bottom layer, three ground planes, and three planes at different supply voltages (1.5, 1.8, and 3.3V). The dielectric thicknesses be- tween the power/ground planes are 3 mils (0.75 mm), which is a fairly popular size. Shown in Figure 2 is a simple PCB created in Mentor Graphics HyperLynx with an area of 16 in 2 (4 x 4 inches), where U1.1 represents the VRM and U2.1 represents the current sink. The current sink is setup to draw 250mA with rise/fall times equal to 250ps. In this baseline case, both the current sink and VRM are connected to layer 2 (VCC1_5), and referenced to all three GND layers. The small yellow circles represent stitching vias used to con - nect all GND layers together. Shown in equation 3 below is the calculation of the effective radius yielding an area of 6.60 in 2 , which is considerably smaller than the total PCB area (16 in 2 ). (3) Using this effective area, we can calculate the effective capacitance as 2.13nF, shown in equation 4 below. In this example, the capaci- tance is calculated based on a single VCC1_5 and GND plane pair (layers 2 and 3) neglecting the holes from the stitching vias. Shown in Figure 3 are the results of this baseline simulation. The peak noise voltage is found to be 91.4 mV located at the current sink. (4) Experiment 2: Further Increasing the PCB Area Oftentimes, simply increasing the PCB area is thought to have a positive effect on the noise voltage since the capacitance is also being in- article Figure 2: The example PCB with one current sink (u2.1) and one vRM (u1.1). The small yellow circles represent stitching vias used to connect the different ground layers together. Figure 3: showing the results of the baseline simulation connecting the vRM and current sink to layer 2 (vCC1_5). Peak noise voltage is 91.4 mv at the current sink. EFFECTIvE DECoUPLING RADIUS continues