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34 The PCB Design Magazine • April 2015 4. Increase the planar capacitance. This is where the tight integration between the ICD Stackup Planner and PDN Planner comes into play. You can add, say, 3M embedded capaci- tance materials between the planes and then import this stackup back into the PDN Planner. This material typically has 20nF/in 2 capacitance and significantly reduces the AC impedance above 1GHz. Ultra-thin laminates are very ex- pensive, but another option is to put two plane pairs, of twice the dielectric thickness, in paral- lel to achieve the same effect at a lower cost. 5. Modify the plane area (capacitance). Ob- viously, a DDR2 1.8V plane will not cover the entire area of the board. By reducing this area to as small as possible (2-square inches) the self-resonance of the plane will be moved up in frequency, reducing the AC impedance at the higher frequency and shifting the peaks. Reduc- ing the plane area however, will also reduce the overall attenuation by increasing the character- istic impedance. Also, keep the area as square as possible. If you create a thin rectangular shape, then the plane resonances will increase due to the different standing wave ratios of the X and Y directions being uneven, thus creating more parallel resonance peaks. The optimization of the PDN is a trial-and- error process that needs to be done in conjunc- tion with the stackup materials to fully exploit all avenues. Suppressing the plane resonance peaks at the odd harmonics, to provide a low impedance profile at higher frequencies, also helps to minimize electromagnetic emissions. Points to Remember • The mainstream market waits for the tech- beyond design LEARNING THE CURvE continues Figure 4: eM radiation overlapped on the PDN plane resonance.