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56 The PCB Design Magazine • April 2015 article creased. After running the simulation on this experiment, we will see that this isn't necessar- ily the case, as it depends on whether or not the plane area is already larger than the effective ra- dius calculated in Equation 3 above. The PCB size is now made 64 in 2 (8 in x 8 in) with all other factors remaining the same. The re- sults of the simulation are shown in Figure 4 be- low with a noise voltage equal to 87.1mV. It's fairly easy to see that the additional capacitance of the plane isn't significantly improving the noise volt- age, as its contributions are outside of the effective area based on the rise/fall times of the current sink. Experiment 3: Increasing the Dielectric Constant, Changing the Layer Spacing In Experiment 2, we found that increasing the power plane size outside of the effective area/ radius had little to no effect on the noise volt- age created at the current sink. What if we were to increase the capacitance of the power plane by either increasing the dielectric constant or by decreasing the spacing between layers? Either or both of these factors would certainly increase the capacitance of the plane pair as well. First, let's increase the dielectric constant of the material. What if we were to increase it by something much larger, say 20? After altering the stack-up to represent a dielectric constant of 20 on all layers (besides the solder mask on the top/bottom layers), the simulation was run and resulted in a peak noise voltage of 72.3mV. At first glance, simply looking at Equation 1 for capacitance indicates that we might expect to see a larger difference in noise voltage when us- ing a higher dielectric constant. To answer this question, the new effective radius using a di- electric constant of 20 is calculated to be 0.67 in, as shown in Equation 5. This radius results in an effective area of only 1.41 in 2 , which by comparison, is much smaller than 6.60 in 2 as it was in the original experiment. (5) What we see happening here is very interest- ing. In this case we wanted to increase the total capacitance of the plane pairs in attempt to fur- ther suppress the noise voltage. By increasing the dielectric constant, we effectively shrink the effective radius, and thus the area that the cur- rent sink can effectively use. The effective ca- pacitance from the original dielectric constant (4.3) is approximately 2.13nF, whereas the new capacitance formed by increasing the dielectric constant to 20 is calculated as 2.13nF also! Run- ning the simulation on this setup yields a noise voltage of 72.3mV, which is improved slightly over 87.1mV. The results of the simulation are shown in Figure 5. It is important to note that there are more complex interactions at work here than just the capacitance of the plane. Modal resonanc- es, spreading inductance, etc., also play a part, which are accurately captured by the field solver. Experiment 4: Decreasing the Spacing between the Planes In this experiment, we will decrease the spacing between the planes to something very small—1 mil. Although these materials are available, they are very expensive and possibly Figure 4: showing the results of experiment 2 above. The area of the PCB (64 in 2 ) is now much larger than the calculated effective area (6.60 in 2 ), yet the noise voltage (87.1 mv) is almost un- affected from the previous simulation (91.4mv). EFFECTIvE DECoUPLING RADIUS continues