Issue link: https://iconnect007.uberflip.com/i/494320
58 The PCB Design Magazine • April 2015 article unavailable depending on the fabricator used. In this experiment, it is done to see if there are drastic effects on the results of the noise volt- age. Additionally, the dielectric constants are set back to their original values of 4.3, and the board is made large (64 in 2 ). The capacitance of this setup is calculated as 6.39nF, and the results of the simulation are shown in Figure 6. Notice that the noise voltage is substantially improved over the previous cases, and even more so than the high dielectric case. What if we set the board size back to 16 in 2 (4in x 4 in) as it was in experiment 1? Af- ter running this simulation, the noise voltage was found to be 32.8mV, consistent with what we thought might happen based on our previ- ous experiments and intuition. The addition- al capacitance formed by increasing the board by 4x the original size has made almost no difference in the total noise voltage because it is outside of the calculated effective area. Experiment 5: Increasing the Number of Power Planes In the previous experiments, we have fo- cused on what could be done when using a sin- gle power plane pair as the main source of PCB capacitance. We have shown that increasing the size of the PCB outside of the effective area has little effect on the noise voltage. Likewise, we have witnessed that increasing the dielec- tric constant also has little effect on the noise voltage as it offsets the added capacitance by shrinking the effective radius. What if we were to use two separate plane pair structures, both at a physical size that is similar to the size of the effective radius? Running this experiment requires a change to the way the current sink and VRM are set- up in the simulation. The stack-up is altered so that layers 6 and 7 are also connected to VCC1_5. Now we will have two cavities form- ing capacitance, both within the effective ra- dius of the current sink. In a simplistic man- or, the capacitance should double, but there is also inductance associated with not only each plane pair cavity, but also between the two cavities. Additionally, we must stitch the planes together with vias for both the GND layers and the newly created VCC1_5 plane on Figure 5: Results of the simulation for experiment 3. The dielectric constant was increased to 20 for all layers. The noise voltage at the current sink has only dropped 14.8mv from the same setup with a normal dielectric constant of 4.3. Figure 6: Results of the simulation for experiment 4. The dielectric constant is 4.3, with the spacing between layers 2 and 3 = 1 mil. The peak noise voltage is found to be 31.2mv, substantially im- proved over the 87.1mv found in experiment 2. EFFECTIvE DECoUPLING RADIUS continues