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22 The PCB Design Magazine • May 2015 sible convenience. Don't assume that specify- ing "dielectric only" will meet your impedance requirements. 2. Do make sure your diff pairs have the same space throughout the run and are of matched length. Don't assume the odd-mode imped- ance is half the differential pair value. 3. Do keep copper 3x the trace width away from the impedance trace if no co-planar coupling is wanted. Don't vary the ground separation dis- tance on the same layer. Keep all the ground separation distances the same on a given layer for all co-planar impedances. 4. Do ensure that all structures have a proper reference plane. Don't place differential pairs over large splits on a plane layer. 5. Do remember Dk decreases as frequency in- creases. Don't assume that all shops know this. 6. Do stick to calling out the desired material by its 4101/ number. Don't assume all materials are the same. 7. Do add any bumps in differential pairs, in an effort to match lengths, somewhere away from the terminations. Don't wrap around a termi- nation point, creating same net spacing viola- tions. 8. Do terminate traces in the center of the pad. Don't terminate traces at the edge of the pad or device. 9. Do consult your fabricator for minimum routing gaps for the desired copper weight. Don't rely on data sheets alone for proper Dk and Df info at a specific speed. 10. Do make sure that what you have specified on the drawing for impedance trace widths ac- tually exists. Don't call out impedances solely by their net names. Please feel free to contact me with any ques- tions or comments. PCBDESIGN THE DO'S AND DON'TS OF SIGNAL ROuTING FOR CONTROLLED IMPEDANCE continues Mark Thompson is in engi- neering support at Prototron Circuits. his column, The Bare (Board) Truth, appears bimonth- ly in The PCB Design Magazine. To read past columns, or to contact Thompson, click here, or phone 425-823-7000, ext. 239. heterointerfaces composed of dissimilar materials have been applied to transistors and leDs. In particular, the best-quality electron sys- tem is formed in gallium arsenide heterostructures, where a unique quantum phase was found at low temperature about 30 years ago. This quantum phase is expected to be applied for a new type of topo- logical quantum computer which possesses dramatically improved computing speed while maintaining tolerance for computational error. researchers at the Quantum Phase electron- ics Center/Department of applied Physics, the Graduate school of engineering at the university of Tokyo, headed by Professor Masashi Kawasa- ki, in collaboration with a group headed by Dr. Jurgen smet at the Max Planck Institute, have fabricated znO heterostructures of unprecedented high quality, and observed the quantum phase in a material other than a Gaas hetero- structure for the first time. This research has been pub- lished in the online edition of na- ture Physics. New Stream for Topological Quantum Computer Research the bare (board) truth

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