16 The PCB Design Magazine • May 2015
shoot) of clock drivers and enhances the signal
quality of a high-speed design.
• Impedance plots are simulated by multi-
ple passes of the field solver to create heads-up
plots of how to adjust the particular variables to
get the desired impedance.
• If you select too low of an impedance, the
di/dt will increase, drawing excessive current
form the supply and no doubt, creating further
power integrity issues.
• Controlling impedance is a trade-off be-
tween trace width, trace (copper) thickness, di-
electric thickness, dielectric constant and trace
clearance.
• The dielectric constant and loss of all ma-
terials varies with frequency.
• Multiple differential pair technologies
should be accommadated on the same sub-
strate.
• The coupling point is where increasing the
trace separation or the dielectric thickness has
little or no further effect on differential imped-
ance. At this point, the impedance rolls off and
the traces become uncoupled. This is also the
point where crosstalk of unrelated signals be-
gins to occur.
PCBDESIGN
References
1. Barry Olney Beyond Design columns:
Embedded Signal Routing, Impedance Match-
ing.
3. Eric Bogatin, Signal and Power integrity
Simplified.
4. Lee W. Ritchey, How and why of obtain-
ing accurate impedance calculations.
5. The ICD Stackup and PDN Planner is
available at: www.icd.com.au.
CONTROLLED IMPEDANCE DESIGN continues
Barry Olney is managing direc-
tor of In-Circuit Design Pty ltd
(ICD), australia. The company
developed the ICD stackup
Planner and ICD PDn Plan-
ner software, is a PCB Design
service Bureau and specializes in board level
simulation.
To read past columns, or to contact
Olney, click here.
Figure 5: Multiple field solver passes produce differential coupling plot.
beyond design
