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May 2015 • The PCB Design Magazine 43 side by nominal 50 μin (1.27 μm) for a new roughness of 175 μin (4.443 μm). Figure 8 shows SEM photos of typical surfac- es for MLS RT foil courtesy of Oak-mitsui. The left and center photos are the treated drum side and untreated matte side respectively. The right photo is a 5000x SEM photo of the matte side showing micro-voids after micro-etch treatment. The data sheet and design parameters are summarized in Table 1. Respective Dk, Df, core, prepreg and trace thickness were obtained from the isoStack software, shown in Figure 7. Roughness parameters were obtained from the Oak-Mitsui data sheet. R z of the matte side after micro-etch treatment (R z = 4.443μm) was used to determine K sr_matte . Keysight EEsof EDA ADS software [14] was used for modeling and simulation analysis. A controlled impedance line (CIL) enhance- ment in version 2015.01 makes modeling the transmission line substrate easy. Unlike earlier substrate models, the CIL model allows you to model trapezoidal traces. Figure 9 is the general schematic used for analysis. There are three transmission line substrates; one for dielectric loss; one for con- ductor loss and the other for total loss without roughness. Dielectric loss was modeled using the Svens- son/Djordjevic wideband Debye model to en- sure causality. By setting the conductivity pa- rameter to a value much-much greater than the normal conductivity of copper ensures the con- ductor is lossless for the simulation. Similarly the conductor loss model sets the Df to zero to ensure lossless dielectric. Total insertion loss (IL) of the PCB trace, as a function of frequency, is the sum of dielectric and rough conductor insertion losses. equation 8 To accurately model the effect of roughness, the respective roughness correction factor (K sr ) must be multiplicatively applied to the AC resis- tance of the drum and matte sides of the traces separately. Unfortunately ADS, and many other commercial simulators, do not allow access to these surfaces to apply the correction properly. The best you can do is to apply the average of (K SR_drum ) and (K SR_matte ) side to the smooth con- ductor loss (IL smooth ), as described above. The following are the steps to determine K SR_avg (f) and total IL with roughness: Figure 9: Keysight eesof eDa aDs generic schematic of controlled impedance line designer used in the modeling and simulation analysis. CANNONBALL STACk FOR CONDuCTOR ROuGHNESS MODELING continues article