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10 SMT Magazine • June 2015 ed circuits (3D ICs) by connecting layers of dif- ferent silicon dies stacked vertically, which can then be integrated into the smallest and densest SoC package. The stacked silicon die can be of the same technology, like DDR memories, or a SoC made up of different technologies or ap- plications. Figure 1 shows the upward trend of IC pack- age pin counts. The declining average area per pin shown in the figure represents the increas- ing pin density of IC packages. The silicon integration trend will reduce the size of the PCBA as more ICs get integrated into one dense IC package. The input-output (I/O) pin count for this dense IC package will be slightly less than the total I/O of all the combined ICs. IC packaging suppliers have increased the rows of solder balls on an array package like BGA to accommodate the demand for more I/O pins. Incrementing a row of solder balls in an array package can yield up to 25% ad- ditional I/O pins. Besides increasing the rows of solder balls, newer array packages have reduced the pitch between the solder balls from 0.5 to 0.4 mm. Packaging array trends show a growth of IC packages with 0.5 mm pitch and smaller, while the demand for IC packages greater than 0.5 mm pitch has stagnated. This a sure sign that PCBA designers are switching to fine pitch array packages to downsize the PCB. Why HDI Technology? A 0.5 mm pitch array package has just enough space to accommodate a 3 mil (0.075 mm) PCB trace in between the solder balls and keep out areas. A 0.4 mm pitch array package, on the other hand—after accounting for the keep- out clearance—has insufficient space to layout a PCB trace between the solder balls (Figure 2), which forces the PCB layout tools to bury the trace in the PCB inner layers rather than plac- ing it on the surface. As a result, the number of PCB layers may increase. This is problematic as the added layers are in direct conflict with con- sumer demand for 'thin' products. One solution to this dilemma is to utilize in- novations in PCB materials and via technology for connecting the different layers within an HDI HIGH-DenSITy InTeRCOnneCT AnD eMBeDDeD BOARD TeST continues Feature figure 1: current trends in ic package pin count.

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