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June 2015 • The PCB Magazine 35 micrometres, strongly limiting the flexibility of the substrate onto which they are placed. The ultra-thin chip packaging technology described later combines a high degree of miniaturization with an inherently flexible chip package. The use of thin-film processing makes it possible to integrate chips with the highest complexity and a fine contact pad pitch. Chip Embedding The Embedded Component Packaging technology from AT&S directly integrates the components in the core layers of the PCB [1] . The technology can be used for the embed- ding of both active and passive components. The main characteristics of the technology are the use of openings in the prepreg layers matching the location of the components and the microvia interconnections to the contact pads of the embedded component. The plated Cu microvia interconnection eliminates the need for solder or conductive adhesives, thus avoiding the associated failure modes. The thickness of the components (100–150 µm for chips, 150–300 µm for passive components) and their pad metallization (copper) need to be compatible with the lamination and met - allization process steps, respectively. A broad range of embeddable passive components are currently available and manufacturers are con- tinuously improving their product range with respect to available values, tolerances, and temperature and power ratings. Bare-die chips are more difficult to procure, especially for lower volumes, but are becoming more and more common. A standard PCB process flow starts with a double-sided core, which is structured in the subsequent process steps and built up to a mul- tilayer construction. In the case of embedding components, a so-called "embedded core" is produced in the first phase of the process flow. The main process steps for embedding of com- ponents are printing of adhesive, assembly of components, lamination and drilling of vias and plated through holes. The suitability of embedding passive components for space ap- plications is currently being investigated in the PCESA project (ESA/TRP) by imec, AT&S and Qi- netiQ Space. Ultra-thin Chip Package To achieve the requirements of form factor and flexibility, the total thickness of the chip package needs to be reduced by an order of magnitude (i.e., less than 100 µm). A suitable candidate is the ultra-thin chip package (UTCP) technology, developed and patented by imec- CMST [2, 3] . This technology consists of an ultra- thin chip, embedded in polyimide layers and contacted using microvias and a fan-out inter- connection scheme (Figure 1). Figure 2 shows the process flow for realizing the UTCP. The process starts from a glass car- rier substrate with a suitable release layer, onto which a polyimide layer is spun. The ultra-thin chip, with a thickness down to 20 µm, is subse- quently placed in the desired location. A second photosensitive polyimide layer is spun on top of the chip and consequently patterned to remove the polyimide in the area above the chip. The second polyimide layer thus acts as a planariza- tion layer for the third polyimide layer that car- ries the interconnection circuitry. This metal layer is realized by vacuum depositing a copper seed layer which is electroplated to the desired thickness. As a final step, the metallization lay- er is patterned, resulting in a flexible interposer Figure 2: Process flow for realizing the ultra-thin chip package. FLExIBLE AND STRETCHABLE CIRCUIT TECHNOLOGIES FOR SPACE APPLICATIONS continues FeAtuRe