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Page 48 of 67

August 2015 • The PCB Design Magazine 49 Probably the only negative, for this configu- ration, is that it will not accommodate multiple power supplies on the lone power plane. Today's high-speed processors and FPGAs require more than six or seven different high current power sources. So if you are pushing the envelope then this configuration is probably not right for you. A recent complex layout that I completed had a total of 13 individual power supplies. As this is becoming the norm, additional power planes need to be exploited and these need to be split to accommodate all 13 supplies plus GND. STACKUP PLANNING, PART 3 continues beyond design Figure 3: standard eight-layer stackup with central planar capacitance using virtual materials. Figure 4: Alternate eight-layer stackup with central split power planes using iTeC iT-180A 2GHz material. 2. The alternate configuration of Figure 5 alleviates the multiple power supply issue but does this by sacrificing planar capacitance. So in order to compensate, for this shortcoming, the PDNs need to have multiple decoupling ca- pacitors with self-resonances close to the funda- mental clock frequency. Also, lower mounting inductance can be achieved by placing these decaps on the top layer so that the fanout vias connect to planes 2 and 5 rather than trans- verse the total layer span. This also helps lower the high-frequency AC impedance.

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