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40 The PCB Design Magazine • October 2015 In the final part of the Stackup Planning series, I will look at 10-plus layer counts. The methodology I have set out in previous col- umns can be used to construct higher layer- count boards. In general, these boards contain more planes and therefore the issues associated with split power planes can usually be avoided. Also, 10-plus layers require very thin dielectrics, in order to reduce the total board thickness. This naturally provides tight coupling between adjacent signal and plane layers reducing cross- talk and electromagnetic emissions. In high-speed digital designs, transient ground currents are the primary source of both unwanted noise voltages and radiated emis- sions. In order to minimize these emissions, the impedance of the ground should be mini- mized by reducing the inductive loop area. In- ductance is directly proportional to the length of the conductor, so keep the loop area as short as possible. To minimize inductance, two conductors (sig- nal traces or ground planes) that carry current in the same direction should be separated. However, two conductors that carry current in the oppo- site direction (such as signal and ground planes or power and ground planes) should be positioned as closely as possible. Both these cas- es also help eliminate crosstalk. Here are some additional rules for high- speed design: 1. Use multiple ground planes, where possible, rather than power planes, in the stackup to isolate signal layers. 2. Place stitching ground vias close to every signal transition (via) to provide a short current return path. 3. Spread numerous ground stitching vias around the board to connect the multiple ground planes through a low impedance path. 4. Don't use ground pours on signal layers as this reduces the impedance of nearby traces. If you must, in order to balance copper, separate the signal and pour by 20 mils. column by Barry Olney in-CirCuiT DeSign PTy lTD AuSTrAliA BEYOND DESIGN Stackup Planning, Part 4

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