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November 2015 • The PCB Magazine 59 ding technology and processes from the printed circuit board industry. With the p² Pack technology, an entirely new technology for manufacturing power mod- ules has become available. So-called lead frames form the basis for this technology. These lead frames are machined to provide cavities for the assembly of power semiconductors. In the next step, these cavities are assembled with power semiconductors. The goal is to posi- tion the surface of the semiconductors in one level with the lead frame. The assembled lead frames are laminated with the help of conventional PCB processes to form a 3-layer structure. This way the bond wires are replaced by a circuit board wiring layer above the chip. The gate contact is implement- ed with conductor tracks and the source pads have a flat design in order to achieve an electri- cal connection as well as favorable thermal dis- sipation of the power. Contacting the upper side of the chips is done galvanically by way of copper-filled blind holes penetrating through the dielectric on the upper side. The semiconductors must have a surface metallization that is compatible with these processes. The design of the p² Pack is to be kept sym- metric as it ensures a minimized pumping ef- fect during thermal cycles. The solid Cu-layers above and beneath the lead frame are a design feature for double-sided cooling of the semicon- ductor while only the lower side must be con- nected to a heat sink. Depending on the lead frame thickness, up to 1/3 of the dissipated power can be distributed via the upper side and can be removed downwards through the pack- age into the heat sink. Smart p² Pack The p² Pack itself can be combined with a logic control board to form a 1:1 substitute for a DCB substrate. Due to the fact that the p² Pack has a height of only 1 to 1.4 mm, it can even be embed- ded in a logic control board. Very short con- nections between the gate driver and the gate contacts of the power semiconductors can be achieved this way. The driver module can be positioned on the control board directly above the power semiconductor while the connec- tion to the gate is carried out with copper- filled interconnections from the outer layer to the p² Pack. A heat sink can be mounted on the bottom of the Smart p² Pack using a thermal interface material. ConDUCTInG Very HIGH CUrrenTS THroUGH PCB SUBSTrATeS AT HIGH AMBIenT TeMPerATUreS ArTiCle Figure 10: connection of gate/source pads with conductor track structures. Figure 12: exploded drawing of the Smart p² Pack functional layers. Figure 11: cross-section of a p² Pack with cu-filled microvias.