Issue link: https://iconnect007.uberflip.com/i/652863
12 The PCB Design Magazine • March 2016 Worse yet, there may be impedance calcula- tions that the customer has based on the 1 oz. finish for outer layers. Increasing the finished copper weight may mean a REDUCTION in your impedance lines. If you have already taken them down to .003" for instance, this may be a problem for the manufacturer. This clarification about what is needed for desired copper can take additional time at the quote process. I am happy to say we are seeing more and more customers, both old and new, embracing this and creating non-conflicting manufacturing notes that allow for a 1 oz. ad- ditional plate. Now, we see notes that read, "1 oz. inner layers, .5 oz starting copper for outers layers (1.5 oz. finished after plate)." That is a good exam- ple of a clear drawing note that does not require additional clarification or send the fabricator down the wrong road for any external imped- ance calculations. It should also be an obvious point that your notes must reflect the data. If you state "IPC netlist compare required," be sure you include the netlist. Likewise, if you have a specific re- gion for placement of a manufacturer logo or date code based on a flag note, make sure that flag note exists. Remember, a good review of the fab notes for their accuracy and validity prior to release is always a good thing! 9. Beware of Conversion Errors Whether it is a conversion error due to for- mat issues or units of measurement rounding, be aware that additional conversion questions can arise at the quote or pre-quote stage. Example: Lets say your drawing specifies .0055" traces on layers 3 and 6 to be 50 ohms +/-10%. This is a nice, round, inch unit measure- ment. Now, let's say your CAD system is metric and it generates a trace width of .005496. Even this slight mismatch can generate questions that take additional time for clarification. In addition, if you have a number of trace widths that are very close, this rounding error can be misinterpreted easily. Additionally, simply specifying specific Im- pedance types by either their name or their net names will not always work. Many manufactur- ers do not have the ability to query a net name for its location to validate impedances, and the same goes for specifying by their type, such as DDR2, SATA, etc. Not all fabricators are familiar with device names. Which leads me to No. 8… 8. Don't Make Assumptions about Controlled Impedances When running simulations for the purpose of signal integrity, try to be within +/-10% . Yes, I know this is a tough one. As a PCB designer, your goal is to simulate impedance to within 10% of your goal. The fabricator should be able to take it the rest of the way. How is this done? Well, typically you will get your marching orders from the engineer who tells you what familiy of materials is nec- essary for the product. If you simply go online and check material PDFs for the purpose of es- tablishing impedances, be aware of at least two things. First, look at the dielectric that the dielectric constant is based on. Many material PDFs are based on .014" or even .028" core, so if your impedance lines are .005" or less, you won't be using these dielectrics. The thicker dielectrics also have higher Dk values, which may create an impedance issue. Let me give you an example: Let's say you have done initial calculation to determine trace widths/spaces based on one of these higher Dk numbers. But in reality, the DK of the dielec- tric required to meet your impedance with your specified line size is vastly lower, which means an ancrease in trace widths. If your design is .1 mm (.00393") traces and spaces, the fabricator has NO ROOM to increase " It should also be an obvious point that your notes must reflect the data. " the top 10 Ways designers can increase profits