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April 2016 • The PCB Magazine 61 long-term thermal reliability of pCb materials to estimate the high-temperature test bound- ary for long-term aging testing of PWB lami- nate material capabilities. The four tempera- tures used varied by material with the Tg (glass transition temperature) of the material being weighed heavily in selection of the upper tem- perature range. Dielectric breakdown voltage was measured at time zero and after 500 hours at elevated temperatures using a Hipotronics 750-2D149 AC Dielectric Analyzer. The % reten- tion of dielectric strength compared to baseline measurements was calculated for each tempera- ture. From these results, the 50% EOL (end of life) was assigned. Due to the nature of short- term testing, it was not used to estimate low temperature boundaries as insufficient material change would be expected when testing at a low temperature for a short period of time. This test is largely based on the testing outlined in IEEE STD 98, Annex A, fixed time frame method (FTFM) of sampling. Phase II: Short-term aging for 1,000 hours at four revised, fixed temperatures was used to develop a thermal endurance graph to extrapo- late and validate 500 hour degradation temper- ature and the 5,000 hour degradation tempera- ture for the 25,000-hour life test. After perform- ing the pre-screen analysis, this data was used to help guide selection of aging temperatures. The 1000 hour test used more aggressive tem- peratures as bounded by the pre-screen data and UL746A procedure. Data was first analyzed in a similar fashion to the pre-screen data to identify potential outliers or worrisome behavior. Arrhe- nius plots were constructed for an initial predic- tion on behavior and performance. For short-term aging for 1,000 hours at four revised temperatures was run next, % retention of dielectric strength was calculated at each temperature. Next, % retention data (one curve per temperature) was plotted vs. time (X-axis). From this data, 50% end of life was determined for each material. A thermal endurance graph was generated in order to extrapolate and vali- date the 500-hour degradation temperature and 5,000-hour degradation temperature to select the temperatures for the long-term operational life test for 25,000 hours. In addition to the thermal endurance test- ing, interconnect stress testing (IST) and highly accelerated thermal shock (HATS) testing were also performed to assess mechanical robust- ness of plated through holes for each laminate. Outside testing services PWB Interconnect So- lutions, Inc. and Integrated Reliability Test Sys- tem, Inc. were used respectively. Phase III: Long-term aging for 25,000 hours at four revised, fixed temperatures was used to develop a thermal endurance graph to extrap- olate and validate 100,000-hour operational life temperature. Testing is approximately 40% complete at this time. Long-term aging will be performed for a minimum of 25,000 hours. Ar- rhenius plots from the six-week test were used to predict a certain degradation percentage in a given time frame. Long-term aging for 25,000 hours at five re- vised temperatures was run next. Again, % reten- tion of dielectric strength was calculated at each temperature. Next % retention data (one curve Table 1: materials Tested.