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76 The PCB Magazine • April 2016 T4, and T5 were selected using both the calcu- lated (predicted) values as well as basic knowl- edge of material characteristics and behavior at higher operating temperatures. Temperatures used in the long-term test are presented in Table 9. Temperature T2 was split into several groupings for laminates D and E to cover additional temperatures based on early re- sults of the T4 and T5 tests. Interconnect Stress Testing (IST) and Highly Accelerated Thermal Stress Testing (HATS) In addition to thermal endurance testing, interconnect reliability was assessed using Inter- connect Stress Testing (IST) and Highly Acceler- ated Thermal Stress (HATS). IST measures changes in resistance of plated- through hole barrels and internal layer connec- tions as holes are subjected to thermal cycling. Thermal cycling is produced by the application of a current through a specific coupon configu- ration. In this technique, the test coupon is re- sistance heated by passing DC current through the internal layer connection to the barrel for three minutes to bring the temperature of the copper to a designated temperature, in this test 150°C. Switching the current on and off creates thermal cycles between room temperature and the designated temperature within the sample. Thermal cycling induces cyclic fatigue strain in the plated-through hole barrels and internal layer interconnects and accelerates any latent defects. The number of cycles achieved permits quantitative assessments of the performance of the entire interconnect. A 10% Change in re- sistance measurement is considered a failure. Although there none of the samples devel- oped a 10% change in resistance, Laminate B Figure 10d: Arrhenius Plots 1/Temperature (K) vs log (Aging Duration, hr.) for laminate D; Calculated 50% Eol. Figure 10e: Arrhenius Plots 1/Temperature (K) vs log (Aging Duration, hr.) for laminate E; Calculated 50% Eol. long-term thermal reliability of pCb materials