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42 The PCB Design Magazine • April 2016 signals. Whereas, the differential strobe is the clock for the data and data mask signals. The timing budget for the data byte lanes and the address group need to be determined and must be spread across the processor package, PCB interconnect and the SDRAM packages. The portion of the timing budget, consumed by the controller IC and SDRAM devices, is fixed and cannot be influenced by the PCB de - signer. The amount of timing budget remain- ing, after subtracting these fixed portions, is all that is left for the board interconnect— which is not much! For a DDR3-1066 SDRAM for instance, data from the JEDEC, JESD79-3E DDR3 standard specifies 25ps for Setup and 100ps for Hold time as in Table 1. Ideally, one should use a simula- tion tool, such as HyperLynx, to measure the setup and hold times to ensure they are with- in the timing budget. However, if you do not have access to an analysis tool, work on 10ps delay, for the routing tolerance, and you can be assured that you are within the margin al- lowing for any derating. That is, providing the transmission lines are matched to 40/80 ohms single-ended/differential impedance, the cor- rect drive currents are being used and the wave- forms are not distorted. Let's face it, it is not that difficult to route each signal to the exact propagation delay given that you have access to each layer's flight time. It is also worth noting that the margin limits can be increased, if the memory interface is not operating at the maxi- mum frequency and/or if a fast memory device is used. Now let's consider a typical 10-layer DDR3 stackup as in Figure 4. There are six routing layers and all the DDR3 signals are routed to 40/80 single ended/differential imped- ance and matched to 2.3 inches in length. In my 2014 column Matched Length does not equal Matched Delay, I cited the difference between the propagation delay of the layers on a PCB. The most dramatic is that of mi- crostrip (outer layers) compared to stripline (inner layers). In this case, the delta between Figure 4: Relative signal propagation for each signal layer on a 10-layer DDR3 stackup. DDr3/4 fLy-By vs. t-topoLogy routing