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14 The PCB Design Magazine • May 2016 more options, such as adding equations into cells instead of hard values, or even creating signal paths to chain a full set of nets together from the beginning of the signal all the way to the end. The levels of complication can become great, but with Intercept's interactive checking throughout the browser, users are steered away from creating impossible configurations. It is imperative to note here that while the automation of design constraints is now readily available in most EDA software, it still remains incumbent on the users to understand what they are doing. While some software vendors might present things in easier or harder to ac- complish ways, it is still ultimately the engineer or designer who will help or hurt the design process. Trends in the Middle Phases of Design Auto-Placement The concept of laying out the components on a board automatically is not new, but it is a constant area of development. Placing compo- nents by functional region, placing them per de- fined groups, or using assisted placement from the schematic has been around in some form or fashion. It is fair to say that most vendors offer some or all of these features to make plac- ing components faster and easier, and that they tend to do the job of saving time well enough. But beyond single component placement, EDA software vendors have moved into the area of blocks of functional components and their circuitry. These circuits are placed in a library for reuse and revision tracking, and are pulled into a layout for placement any number of times. Many vendors handle the reuse of blocks of circuits through a glorified copy-and-paste mechanism, which often presents problems because the copies are not traced back to their original, or they are not checked as part of the whole physical board. Intercept's strategy was to develop a fully intelligent and reusable block of circuitry in Pantheon, called a "block geometry." Areas of circuitry that are used over and over again with little modification can be defined as block ge- ometries and placed into the layout as a block array in a matter of seconds, and modified where needed without losing its links back to its parent block geometry. This allows major revisions of the block to be updated across the entire layout, with individual modifications (such as moving a component to avoid a drill hole) preserved. Repetitive circuits can even be defined as blocks within blocks, thus allowing design changes to be done in a matter of minutes. This technology has been used by Intercept's customers to place entire block panel arrays in minutes, whereas in the past it might have taken days. Autorouting Autorouting has been around for a very long time. But the trends surrounding it are changing. The simplest autorouters use a mixture of net class spacing and width constraints along with a layer's specified autoroute directions (horizon- tal/vertical, axial/diagonal, etc.), and attempt to generate successful pin-to-pin routes. These au- torouters tend to create some nasty routes that are nowhere close to the desired result. But it is generally accepted that while these routers re- quire further work to fix some of the anomalies that occur along the way, they are still saving time in the end. But for the growing number of high density boards, or boards with diff pairs and high speed tuning, there is a movement toward throwing THE STATE OF THE ELECTRONIC DESIGN AUTOMATION NATION Figure 3: Example of design reuse as applied to a panel array design.