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26 The PCB Design Magazine • May 2016 based on previous capacitor availability and pa- rameter selections. A selection of predefined library compo- nents could be offered, based on an initial bill of materials, and pre-placed on the schematic predicting the designer's requirements. IBIS models could be automatically assigned to each chip, based on the part number and all the in- terconnecting transmission lines identified. The IBIS model's source and load impedances could be extracted to assign the required impedance and terminations to each individual transmis- sion line. Also from this, the board stackup could be created based on previous designs, with similar technology, selecting dielectric materials, from a well maintained library, sourced from the pre- ferred fabricator availability, dielectric loss and bandwidth requirements. Data and address bus- ses together with clock/strobe different pairs, defined at the schematic entry level, could be assigned to certain layers in order to minimize crosstalk, electromagnetic emissions and return path loops. Power plane shapes could be auto- matically defined based on component place- ment and on the pins that need to be connect- ed, allowing for DC drop and maximum current supply. Memory blocks— whether they be syn- chronous, asynchro- nous, source synchro- nous, clock-forwarding or embedded clock— could be recognized and standard design rules deployed. Busses and interfaces could be also analyzed and recognized. The entire design rule set could be built from a combina- tion of these require- ments and those learnt from previous similar designs. Functional blocks that the designer is working on, could be scrutinized in order to anticipate which blocks might be useful in future designs and these could then be made available to other designers on the corporate intranet. A database of reusable placement and routing blocks could be made available so that the intelligent database can readily identify a suitable block to drop into the design–the se- lected block could then be automatically adjust- ed to the specific needs of each instantiation. Intelligent forward and back annotation would be a definite godsend. Traditionally, the schematic capture and PCB layout software were developed as separate applications coupled by the annotation process. Why can't we have a common database for both schematic and PCB totally eliminating the constant need to update in one direction or the other? When an ECO is implemented on the PCB, the schematic should instantly know and understand the changes and vice-versa. Over the years, forward and back an- notation has been one of the most frustrating and time-consuming issues. The intelligent database could suggest place- ment of critical components based on the es- tablished design rules, matched delays of bus- ses and define routing strategies based on the technology used. But, will autonomous routing ease PCB gridlock? Placement changes could be THE CASE FOR ARTIFICIAL INTELLIGENCE IN EDA TOOLS Figure 2: SMT assembly production line (Courtesy Juki).

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