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46 SMT Magazine • June 2016 by Stephen Las Marias I-CONNECT007 In an interview with SMT Magazine, Vi Tech- nology's Jean-Marc Peallat, vice president global sales, and Chong Choon Hee, Asia sales appli- cation manager, speak about the solder paste inspection (SPI) challenges when it comes to tighter tolerances and finer lines and pitches in board assemblies, and the latest innovations happening in the SPI space to help customers address these issues. Stephen Las Marias: Jean Marc, what are the challenges that your customers face when it comes to SPI as tolerances become tighter and pitches smaller? Jean-Marc Peallat: Your question raises two challenges. First, with miniaturization and the need for more intelligence, PCBs are becoming very dense and therefore, pads are becoming smaller with less space in between. Traditional SPI uses "region of interest" (ROI) surrounding the pad. This one defines the area of the mea- surement, where the paste deposit should be, but also the location of the z-references. With size and pitch becoming smaller, the ROI is get- ting very small and very close to the pad. It be- comes more and more difficult to define stable references that guarantee good measurement. Also, it may come across the ROI border. For traditional SPI, this results in a bridge defect. With a large field of view, our new SPI is not us- ing ROI surrounding pads, and is not limited or impacted when pads are getting small and close to each other. The other challenge concerns the calcula- tion and the setup of parameters. Traditional SPI uses tolerances defined by a percentage of the theoretical volume or height. It is like one size fits all, tolerances for 0402 will be defined the same way than as 01005. Unfortunately, the physics of the printing process is not as simple as this. Effective transfer, the ratio between the- oretical volume and real deposit, varies widely SPI Parameter Considerations for Tighter Tolerances FEATURE INTERVIEW Jean-Marc Peallat Chong Choon Hee

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