Issue link: https://iconnect007.uberflip.com/i/688506
June 2016 • The PCB Magazine 31 HIGH-THROW ELECTROLESS COPPER—NEW OPPORTUNITIES FOR IC SUBSTRATES AND HDI MANUFACTURING All measures sum up to an actual line width in- crease of 75% from 2.0 µm to 3.5 µm. Throwing power is an essential requirement for electroless copper processes for enhanced fine line capability, but not the only one. Oth- er relevant performance characteristics are the adhesion of dry films onto the electroless cop- per deposits and the adhesion of the deposited layer itself to the increasingly flattening bare laminates. Both factors directly affect the over- all process yield rate. The picture changes for HDI board manufac- turing. The contemporary manufacturing tech- nique for high-end HDI PCBs is panel plating in horizontal application mode. Leading manu- facturers achieve approximately 35/35 µm L/S by applying standard 17 µm copper clad base materials and about 18–20 µm electrolytic cop- per plating. In order to reduce the etch depth required for the pattern formation and thus elevate the L/S resolution significantly down to 20/20 µm, manufacturers intend to change their current production process from panel to pattern plating and more precisely to the ad- vanced modified semi additive process (AMSAP) technology (Figure 2). As a consequence, the ex- isting manufacturing equipment and processes needs to be modified to cope with the new chal- lenges that come along with this approach. The alternative, to push the panel plating technol- ogy to its limit by applying a thin copper clad base material—similar to the one used for AM- SAP—and by the reduction of the electrolytic copper layer, is still limited in L/S resolution of above 20/20 µm and therefore no viable option. As can be seen in Figure 3, the dry film lamination and development steps within the AMSAP process are located directly after the electroless copper deposition in contrast to the panel plating process where the dry film is ap- plied after the final electrolytic copper build-up. This difference in the process sequence has an Figure 1: Impact of the electroless copper thickness on L/S resolution for IC substrates based on SAP technology.