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July 2016 • SMT Magazine 75 formance. Hence, some statistical method is re- quired to determine the minimal requirement of sample size needed within allowable resources. Figure 7 shows the warpage magnitude ob- tained from multiple random sampling simu- lations by selecting a pre-defined sample size from a pool of units. The pool of data was ob- tained by combining the earlier warpage mea- surement for as is, bake and MET 9 days for a given product candidate to capture the poten- tial noises that may exist in a manufacturing environment. From the graph, the mean warp- age and standard deviation will fluctuate more than 5% when less than five samples are chosen from the pool. The mean warpage and standard deviation are kept within 5% when sample size is nine or more. The same finding was estab- lished when repeating this sampling simulation on other products. This seems to suggest that a minimum of three samples—as stipulated in JESD22-B112A 8 —may not be enough in some cases. Furthermore, the sampling method may need to consider multiple assembly batches to establish a representation of the warpage mag- nitude range that is useful for component board assembly yield assessment 6, 7 . The dynamic warpage characteristics ob- tained for PoP bottom and PoP memory pack- ages demonstrate that the electronic industry is creating packages with broad dynamic warpage characteristics that depend on the entire design and material set used. The warpage magnitude at peak reflow temperature can play a major role in surface mount yield, a fact with should be re - flected in JEDEC or any industry guidelines. Al- ternatively, there are many customized compo- nent board assembly recipes that may be used to mount packages 6 . The impact of as is, bake and MET requires constant evaluation to ensure the dynamic warpage characteristics are understood. The impact of more complex warpage shapes like "M" and "W" in PoP stack-up analysis re- quires more focus to establish the fundamental of component board assembly yield assessment. Summary and Next Steps The work here covered a very broad dynamic warpage characteristic of different PoP bottom and PoP memory packages. The impact of as is, bake and MET were quantified and requires more consistent characterization across compo- nent suppliers to establish the sensitivity to the precondition environment in order to mimic potential component board assembly. The sam- ple size needed to establish a representation of warpage and the use of a statistical tool in pack- age warpage reporting requires more focus if the attempt is to correlate with component board Figure 6: Effect of as is, bake, MET 9 days to package warpage at room and peak reflow temperature for PoP memory packages. PACKAGE-ON-PACKAGE WARPAGE CHARACTERISTICS AND REQUIREMENTS