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38 SMT Magazine • September 2016 of confidence in the conditions under which components will reliably self-mitigate. Prior work concluded that for a specific set of process conditions, board finish, and pad design, self- mitigation can be predicted by the geome- try of the component terminations [1] . It is not clear, however, how these results apply for dif- ferent manufacturing processes, board finishes, and pad sizes. Without this understanding, the only reliable means for systems integrators to be confident that self-mitigation has been achieved on a given set of assemblies is to dupli- cate the conditions of the prior study, or to per- form direct measurements on the as-received hardware. The existence of this knowledge gap prompted the Pb-free Electronics Risk Manage- ment Council (PERM, IPC Committee 8-81) to initiate a project in 2014 under IPC task group 8-81F, to perform a study. The first phase of that study has been completed, and this report describes that study and the results to date. Design of Experiment The task team agreed to perform a new set of experiments involving the manufacture of identical sets of test vehicles at a number of dif- ferent locations, all assembled to the require- ments of IPC J-STD 001, Class 3. For simplic- ity, and to permit direct comparison with the results of the prior study, it was decided to use Table 2: Component packages used in the study. Table 1: Design of experiment. MITIGATION OF PURE TIN RISK BY TIN-LEAD SMT REFLOW

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