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14 The PCB Design Magazine • September 2016 ture, electronic enclosures, sche- matic capture, PWB design (rig- id, flex, rigid-flex), and cabling. Shaughnessy: Tell us about JMC Design Services, and what led you to start your own company? Cardone: I worked at JPL from 1983-2005. At that time factors all converged to allow my fam- ily to make the move to Grenada where we have a small ranch, for the purpose of raising horses. If I could have done that and stayed at JPL I would have, but it's 650 miles away. The next best thing was to contract to them as a remote associate, and this I've been doing for JPL and a number of other clients since 2005. Shaughnessy: So you were at JPL for 22 years, when they were just getting into EDA tools. What were some of the biggest challenges you faced (technical, bureaucratic, etc.) during that time? Cardone: When I started at JPL in the design room, they were just getting started in MCAD with CV CADDS3. JPL is a matrix organization, and I am not certain of the state of EDA tools in the sections with an EE focus. It may have been very rudimentary as I do recall creating many schematics and PWBs for the Galileo S/C. CV was a unique platform because it did it all. You could create an electronics enclosure, add a PWB to it, link the PWB to a schematic net-list from a schematic created in CV, and then place and route the PWB. CV is still be- ing used in the ship-building industry because it is very adept at large assemblies. It was later purchased by ProE, hence its decline and JPL's search for a replacement. I believe that the fact it was being used at the time of my start at JPL fostered my inclination to cross the boundaries that typically exist between mechanical, electri- cal, systems, thermal, etc. On the MER (Mars Exploration Rover) project I was a member of the mechanical, systems, and electrical engi- neering teams. At JPL these were few bureaucratic challeng- es. It's a marvelous place, and more of a campus environment than a commer- cial engineering firm. The one challenge I felt is that the vast majority of funding is tied to a specific project, so we could not be a Bell Labs where you have the luxury of playing around until you hit on something. An axiom is that technology used on flight projects must have a high TRL (technology readiness level), and how do you get a high TRL? By being demonstrat- ed on a flight project, of course! I cannot complain about the progress that EDA tools have made over the years. Having started on a light table, being able to insert or delete a trace with a few clicks is amazing. Even in the early '80s, CV had gate and pin swap, and back annotation. But it was cer- tainly slower. There were many times I babysat a computer overnight as it chugged along. At that time (and today) we were limited in our selection of components because of their fault tolerance and radiation hardness. It was very rare that we spent the mass to radiation-shield a component. It had to arrive at the dock hardened. So, for ex - ample, Galileo PWBs were designed with robust CMOS logic in flat packs. We still occasionally use flat packs, and even some DIPS. The environment: One major concern in both mechanical and EDA design is the severe thermal cycling seen by both earth orbiting and space probes. With mechanical design (which includes printed flex cabling) attention has to be given to the CTE of all dissimilar materials with an interface. This effects bolted joints, necessary machining tolerances, selection and use of potting materials, and on and on. As you know, the X-Y CTE of polyimide has been tuned to be close to that of aluminum, but since it has a ~constant bulk CTE, plated through-holes that see large delta T can crack due to the large difference in the CTE of CU and CTE-Z of poly- imide. Let me focus on PFC (printed flex circuit) for a moment. Its optimal design isn't necessar- ily the same as in a rigid, or rigid-flex design. Here are a few examples: First, in a PFC, for con- trolled differential impedance, an off-set broad- JOHN CARDONE ON DESIGNING FLEX FOR SPACECRAFT John Cardone