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58 The PCB Design Magazine • September 2016 good if the change from the thermal junction to ambient is within 10% of measurement results. How do the details represented by the sim- ulation model help to improve a design? Let's look at a detailed analysis of two different de- signs of an IC onto a PCB where only the top layer and number/position of the thermal vias varies (Figure 6). The modeled PCB is approximately 1.6 mm thick with six layers (outer layers = 67 µm thick; inner = 95 µm thick) (Figure 7). The IC is an SOT223 (surface mount, 4 pin) package modeled with nominal values. The 15 thermal vias are 300 µm inner hole and 25 µm copper- plating thickness (modeled as square section). It has 1-W power loss at the inside junction and a 25°C ambient and cooling block temperature. In Figure 6 and 7, the "bad" (left image of top layer) and "good" (right image of top layer) designs can be differentiated by analyzing the detailed models. In this first example of a bad layout, the base has 15 thermal vias. Analysis results shows that the thermal junction maxi- mum temperature is 64.6 °C. 0.69 W is trans- ferred by conduction into the PCB top layer (the rest, 0.31 W, is going outside the junction through pins 1-2-3 by conduction or outside the encapsulant by convection) (Figure 8a). Only 0.40 W is transferred into the thermal interface material (TIM) through the 15 thermal vias (Fig- ure 8b). This is inefficient thermal via use. The second example of a bad layout uses nine thermal vias instead of 15. Analysis re- sults shows that the thermal junction maxi- mum temperature is 65.1 °C (+0.5 °C). 0.69 W are transferred by conduction into the PCB top layer. The rest, 0.31 W, is transferred outside the junction through pins 1-2-3 by conduction or outside the encapsulant by convection (Figure 9a). Only 0.39 W is trans- ferred into the TIM through the 9 thermal vias (Figure 9b). Removing six of the vias has little affect (ΔT = 0.5 °C). The first example of a good layout also has a base of 15 thermal vias. Analysis results shows that the thermal junction maximum tempera- ture is 45°C. 0.87 W is transferred by conduc- tion into the PCB top layer by pin 4. The rest (0.13 W) is going outside the junction through pins 1-2-3 by conduction or outside the encap- sulant by convection (Figure 10a). 0.60 W is transferred into the TIM through the 15 ther- mal vias (Figure 10b). This is a much more ef- ficient use of the thermal vias. Figure 6: In the IC for which thermal behavior is simulated, only the top layer is different between the two designs. THE FUNDAMENTALS OF IMPROVING PCB THERMAL DESIGN