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16 SMT Magazine • November 2016 David Geiger, Anwar Mohammed and Jennifer Nguyen* FLEX Abstract Quad flat no-lead (QFN) packages have be- come very popular in the industry and are widely used in many products. These pack- ages have different size and pin counts, but they have a common feature: a thermal pad at the bottom of the device. The thermal pad of the leadless QFN provides efficient heat dissi- pation from the component to PCB. In many cases, a thermal via array under the compo- nent is used to conduct heat away from the device. However, thermal vias can create more voids or result in solder protrusion onto the secondary side. This paper discusses our study on the im- pact of via size and via design on QFN voiding and solder protrusion. Does a small via prevent the solder to flow to the other side? How should the via be designed? Which via type will have less of a voiding issue? A comprehensive experi- ment was designed to try to answer these ques- tions. Different QFN types, via design, via sizes, via pitches and stencil design were studied us- ing three different board thicknesses: 1.6 mm, 2.4 mm and 3.2 mm. Introduction Quad flat no-lead package is designed so that the thermal pad is exposed on the bottom of the component. This creates a low thermal resistance path between the die and the exte- rior of the package and provides excellent heat dissipation from the component to PCB. Ther- mal vias in the PCB thermal pad are typically used to conduct the heat away from the device and to transfer effectively the heat from the top copper layer of the PCB to the inner or bottom copper layer or to the outside environment. A cross-section view of QFN and PCB thermal vias is shown in Figure 1. There are several publications about the PCB layout guidelines for QFN packages requir- ing thermal vias [1-2] . Some recommend thermal vias in the solder mask defined thermal pad [2] while others place the thermal vias directly on FEATURE

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