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50 The PCB Magazine • November 2016 rates will reduce resin smear. On the negative side, high feed rates can cause burrs, hole wall roughness and debris in the holes. Per standard drilling guidelines, smaller di- ameter holes and thicker boards require lower chip loads. In part 2 on this subject, I will pres- ent more in-depth information on drilling and its ramifications on PTH quality and reliability. Summary When this monthly column first appeared on the pages of The PCB Magazine, five years ago, it was suggested that producing high-qual- ity, high-reliability printed circuit boards re- quires strict adherence to processing guidelines along with vigilance in understanding and ex- ecuting on the principles of trouble-shooting. A thorough understanding of each of the process steps is critical in minimizing or eliminating non-conforming defects—the ones that cost the fabricator money and can lead to lost custom- ers. Each process must be deeply understood on its own merits. Mechanical drilling is one such process. PCB Michael Carano is VP of technol- ogy and business development at RBP Chemical Technology. To read past columns or to contact Carano, click here. VIA FORMATION AND DRILLING MECHANICS, PART 1 For more than a de- cade, engineers have been eyeing the fin- ish line in the race to shrink the size of com- ponents in integrated circuits. They knew that the laws of physics had set a 5-nanometer threshold on the size of transistor gates among conventional semicon - ductors, about one-quarter the size of high-end, 20-nanometer-gate transistors now on the market. Some laws are made to be broken, or at least challenged. A research team led by faculty scientist Ali Javey at the Department of Energy's Lawrence Berkeley National Laboratory has done just that by creating a transistor with a working 1-nanometer gate. For comparison, a strand of human hair is about 50,000 nanometers thick. "We made the smallest transistor reported to date," said Javey, lead principal investigator of the Electronic Materials program in Berkeley Lab's Ma - terials Science Division. "The gate length is consid- ered a defining dimension of the transistor. We dem- onstrated a 1-nanometer-gate transistor, showing that with the choice of proper materials, there is a lot more room to shrink our electronics." The key was to use carbon nanotubes and molybdenum disulfide (MoS2), an engine lubricant commonly sold in auto parts shops. MoS2 is part of a family of materials with immense potential for applications in LEDs, lasers, nanoscale transistors, solar cells, and more. The findings were published today in the jour - nal Science. Other investigators on this paper include Jeff Bokor, faculty senior scientist at Berkeley Lab and professor at UC Berkeley; Chenming Hu, professor at UC Berkeley; Moon Kim, professor at the University of Texas at Dallas; and H.S. Philip Wong, professor at Stanford University. The development could be key to keeping alive Intel co-founder Gordon Moore's prediction that the density of transistors on integrated circuits would double every two years, enabling the increased per - formance of our laptops, mobile phones, televisions, and other electronics. Smallest. Transistor. Ever.

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