Issue link: https://iconnect007.uberflip.com/i/746712
November 2016 • The PCB Magazine 25 • Any signal routed on the blind via layers will not need to have a buried via, thus opening up route space on the buried via layers as well • The disadvantage is that blind and buried via stackup is slightly more expensive than a through-via stackup Example of Shifted Blind Vias An excellent example of shifted-aligned- via pattern is the Xilinx Virtex-4 and Virtex-5 FF1760 series FPGA with 1760 pins and a 1 mm pin-pitch from an article by Pfeil [5] . Xilinx Ap- plication Data sheets show the use of six-signal layer to breakout their device. In Pfeil's article, using the shifted-aligned-via pattern to form boulevards, he completed the breakout is only two signal layers. The stackup is also seen in Fig- ure 6 and is a common and cost effective IPC- Type II 12-layer HDI. To understand how this was accomplished requires you look closely at both the HDI stack- up and the aligned-shifted blind vias. This close- up can be seen in in Figure 7. Two rows of the FPGA pins fanout to layer 3 (with a skip via-for the 50 ohms single-ended Rocket I/O) and the next two rows fanout to layer 2 then drop to the INNOVATIVE USE OF VIAS FOR DENSITY IMPROVEMENTS Figure 6: Example for a Virtex 5, 1760 pin FPGA. Three alternative surface breakout using 'swing vias' [7] . Figure 7: Example for Virtex 5, 1760 pin FPGA, Layer 3 and Layer 5 breakout boulevard routing with stackup view [7] .