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18 The PCB Design Magazine • November 2016 ated with the smaller depth of the drilled hole and smaller plating aspect ratios. Shaughnessy: What are your thoughts on back- drilled vias? Wolf: Back-drilled via structures are common to- day in high frequency multilayer PCB applica- tions. Back-drilling is used to remove that portion of a through via plated barrel without inner layer connections that would act as an antenna stub. Multiple depth back-drill via structures have been included in both the 14-layer and 24-layer PCQR 2 sequential lamination designs since January 2010. The reliability of back-drill via holes is very simi- lar to through via holes of the same drilled diam- eter. The biggest challenge is drill depth control. Shaughnessy: Are you seeing many landless vias, via-in-pad, or thermal vias? Wolf: These types of via structures have not been part of the standardized PCQR 2 designs. The database subscribers have not specifically requested that these types of via structures be included in the test panel designs. With land- less vias and via-in-pad, the major challenge is via registration. Shaughnessy: What should PCB designers know about vias and via design? Wolf: There are at least three areas of concern when evaluating the design of via structures: A. Both via structure formation capability and uniformity must be controlled and repeat- able before initiating via reliability studies. For the most reliable PCB designs, use the largest via drill diameter that the PCB design will allow; this yields the lowest via hole plating as- pect ratio that is easier to process. With surface mount components that have a high number of pin-outs, staggered or stacked microvia struc- tures might be required to successfully complete cir cuitry routing and interconnect requirements. CAT'S DAVID WOLF ON VIA RELIABILITY ANALYSIS Figure 4: Blind, through and stacked vias shown after thermal cycling.