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34 SMT Magazine • January 2017 to fail before corner joint A meaning that simul- taneous failure of both channels is anticipated to be solder failure in the corner joint (Figure 3). The remaining solder joints in the assembled solder joint array (i.e., beyond the two moni- tored joints in each corner) are stitched togeth- er in a single test net. A similar board design was used in a pre- vious drop reliability study 14 . Some effects of solder alloy on drop lifetime were observed in that study. However, the dominant failure mode was laminate pad cratering. Shock in- duced cracks propagated in the board laminate rather than through the solder joints of inter- est. For an alloy study, it was considered desir- able to compare failures occurring in the sol- der alloys of interest rather than failures in the underlying laminate material. The board de- sign used in this study strengthens copper sig- nal traces and pads as well as uses solder mask defined pads for both component and board side (Figure 4) to promote solder joint failure. Failure is identified by significant increase of electrical resistances through an event detec - tor. While the test circuit is designed to pro- vide some indication of failure mode through event detection, the actual failure mode is al- ways confirmed by cross-sectional observation (Figure 4). Drop Test Apparatus Service condition "F" of JEDEC Mechanical Shock Standard (JESD22-B104C) is applied in this study: 900G acceleration peak value, 0.7ms pulse duration, and 386 cm/s (152 in/s) veloc- ity change. The drop test apparatus is a Lans- mont shock table illustrated schematically in Figure 5. To expedite testing of the large sam- ple quantities required by this study, mounting fixtures for the simultaneous drop of four test boards were included on the table surface. Each mounting fixture consisted of four standoff posts for the corner mounting holes the board. They were arranged in a two by two array cen- tered on the table. EFFECT OF SOLDER COMPOSITION, PCB SURFACE FINISH AND SOLDER JOINT VOLUME Figure 2: Channel traces at one corner (A) of the BGA array. Red line represents the attached component chain. (Image from previous study 14 using NSMD pads.) Figure 4: (a) Redesigned test board and (c) its failed joint; (b) previous test board and (d) its failed joint. Figure 3: Illustration of event detection for failure mode.