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28 The PCB Magazine • January 2017 Plating Plating and surface finish applications are not without their own set of challenges but these manufacturing processes also effect the electrical test theatre. Microvias, high-aspect ratio plate quality, and surface finish all have their own challenges in ET. Let's face it, the largest challenges regarding plating involve the detection of voids. Whatev- er type they may be is insignificant in ET as the detection is foremost the main focus. Unfor- tunately, with standard ET detection processes many partial voids go undetected. This also can be said for a barrel that is voided outside of the electrical test signature. The undetected partial void is usually the "taper plate" or "narrowing" void. These defects usually have adequate plating near the annular rings towards the outer layers but then narrow as they reach the center of the barrel. Figure 1 shows a typical taper plate defect. This type of defect usually will not fail the standard ET continuity test. There is sufficient plating in the barrel to pass the electrical signal within the continuity threshold (usually 10–20 ohms depending on performance class). For the capture of anomalies such as this it is recom- mended that a 4-wire Kelvin sampling test be performed. This type of continuity test is de- signed to capture minute fluctuations in barrel resistivity. These measurements are in the milli- ohm (mO) range. Microvias pose another challenge to ET. Usually these are buried (manufactured in the sub-part level) and have no direct landing pad accessible from the outer layer. In Figure 2, we Plating and Surface Finish: The Challenges to Electrical Test FEATURE COLUMN: TESTING TODD by Todd Kolmodin GARDIEN SERVICES USA Figure 1: Taper plate defect. Figure 2: Microvia void.

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