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34 The PCB Design Magazine • January 2017 The impact of lower core voltages and faster edge rates has pushed the frequency content of typical digital signals into the gigahertz range. Consequently, the performance of decoupling capacitors, that are required to complement the power distribution network (PDN) and curb signal induced fluctuations, must also be extended up into this range. However, rudi - mentary design rules, adequate for frequencies below 100MHz, may not be suitable for today's high-speed digital circuits. The symptoms of an inadequate PDN design are increased power supply noise, crosstalk and electromagnetic ra - diation leading to poor performance and pos- sibly intermittent operation. In most cases, conventional design guide- lines recommend that the decoupling (or by- pass) capacitors be placed on the bottom side of the PCB, under the BGA, for closest proxim- ity to the IC. However, decoupling is not the process of placing a few random capacitors ad- jacent to each IC power pin. But rather, it is the process of placing an RLC network to supply the transient switching current and to provide a return current signal path back to the sour ce. A capacitor's equivalent circuit is basically a series capacitor, resistor and inductor as illus - trated in Figure 1. These are referred to as the capacitance value, ESR and ESL respectively. The primary design consideration is the by Barry Olney IN-CIRCUIT DESIGN PTY LTD / AUSTRALIA PDN–Decoupling Capacitor Placement BEYOND DESIGN Figure 1: A capacitor has series capacitance, resistance and inductance.

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