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20 The PCB Design Magazine • January 2017 knows that their design—their output data— serves as the hub of all of the manufacturing processes. It is so very important that insuffi- cient or vague or unmanufacturable design data never be tossed over the wall to other stakhold- ers. Providing insufficient copper-to-edge spac- ing is like a missing spoke on a racing bicycle's wheel. It needs to be addressed before the race begins. If addressed during the race, the rider may stop suddenly, surely affecting the other riders behind him. But how does a designer know what copper- to-edge spacing value is adequate for keeping the bare copper stable and protected? An out- dated rule of thumb back in the day was .050", but times have changed and manufacturing capabilities have too. Packaging densities have increased wildly and board real estate has never been more valuable. So, if asked by someone in your design team how close the copper can get to the edge, what is a proper response? Hopefully, you can pull a copy of IPC-2221 off your shelf and turn right to section 10.1.1. Here you will see an industry standard recommendation which takes into ac- count not only industry standard panel process- ing, but electrical clearances as well, as shown in Figure 4. Figure 2: Fab note allowing CAM department to modify copper-to-edge spacing. Figure 3: Example of robust copper-to-edge clearance on a low-density design. Figure 4: Recommendation found in IPC-2221, section 10.1.1. TRUE DFM: TAKING CONTROL OF YOUR EDA TOOL