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36 The PCB Design Magazine • January 2017 parasitic series inductance of the capacitor it- self and its associated mounting and via induc- tance. The parasitic series inductance of a de- coupling capacitor acts like a small inductor in series with the capacitor. At higher and higher frequencies, the impedance of this parasitic in- ductance becomes larger and larger (Figure 1), until it finally dominates the performance of the component. In the critical 100MHz – 1GHz band, the effectiveness of a typical decoupling capacitor is determined almost entirely by its series in- ductance. This is the frequency band now be- ing used increasingly by digital logic. For ideal performance, low series inductance is required. However, the series inductance of a capacitor is not only determined by its ESL, but rather al- most entirely by the layout of the capacitor's mounting lands and its associated fanout vias. The exact location of the capacitor is unimport- ant (providing it is within a 2" radius of the IC) as the plane inductance is negligible. Every time the signal edge rates double, we become twice as dependent on these layout details. If a product radiates too much in this region, the most effective way to reduce noise is to improve the layout of the decoupling capacitor lands and to reduce the via loop area. Improving the layout reduces the effective inductance of the components, leading to a direct reduction in power and ground noise. It is the inductance of this current path that creates ground (supply) bounce. If the layout cannot be modified, then the following alternatives may suffice: PDN–DECOUPLING CAPACITOR PLACEMENT Figure 2: A 16-layer stackup with three pairs of planes.