Issue link: https://iconnect007.uberflip.com/i/773715
38 The PCB Design Magazine • January 2017 1. Add more capacitors, but this will only add to the expense and consume more real estate. 2. Change the capacitor to a reverse geom- etry package with lower ESL – e.g. use a 0204 instead of a 0402. 3. Use a thin, high-dielectric constant (Dk) material between the planes, which adds more plane capacitance. 4. Use embedded planar capacitance mate- rial. This technology allows for a very thin di- electric layer (0.24 – 2.0 mil) that provides dis- tributive decoupling capacitance and takes the place of many conventional discrete decoupling capacitors to some extent. So, let's look at a typical 16-layer multilayer PCB with three plane pairs as in Figure 2. The to- tal board thickness is 60.92 mils and the planes are symmetrically positioned in the stackup. Placing a BGA on the top side of the board and the decoupling capacitors directly under the BGA on the bottom side would require twice the total board thickness for the entire loop (power and GND vias) for each capacitor. In this case, the plane inductance can be ignored as it is insignificant. However, this is accounted for in the top mounting configuration by add- ing spreading inductance as the decaps cannot be placed directly under the BGA. The follow- ing calculations give the total loop distance for each configuration (Figure 3): Amazingly enough, the bottom mount de- cap has about twice the current loop area as the top mount decap which equates to about twice the loop inductance. For example, a 22nF 0402 capacitor (Figures 4 and 5) has inductance of 1.28nH mounted on the top and 2.85nH on the bottom side. The most important specifica- tion for a decoupling capacitor is its series in- ductance and here we have more than doubled that inductance by following conventional de- sign rules. These rules have been in use for over 25 years, so maybe it is time for an update! Figure 4 illustrates the effective AC imped- ance of the bottom mount decoupling capaci- tors, including via loop inductance, of the 16-layer PCB extracted from the ICD Stackup Planner. To keep the impedance below the tar- get impedance, all the way up to 1GHz, requires 82 optimized decaps. Please note that I have also used close coupling (2.5 mils) between the planes which dramatically improves the planar capacitance. Figure 5 illustrates the effective AC imped- ance of the same decaps mounted on the top side of the board. Note how low the impedance is at the top end. Where the bottom mount decaps were below the target frequency up to 1GHz, the top-mount decaps are below to 2.5 times the fundamental frequency (2.5GHz). And, the capacitor count (Table 1) can be re- duced from 82 (bottom mount) to just 38 (top Figure 3: Decoupling capacitors placed on bottom vs. top of board. PDN–DECOUPLING CAPACITOR PLACEMENT