Issue link: https://iconnect007.uberflip.com/i/773715
40 The PCB Design Magazine • January 2017 PDN–DECOUPLING CAPACITOR PLACEMENT Figure 4: PDN analysis of the bottom mount decoupling capacitors. Figure 5: PDN analysis of the top mount decoupling capacitors. mount) with greater bandwidth at half the cost and assembly time and superior performance. This potential gain depends on the layer count and how the planes are arranged in the stackup. If the planes are central, as in a typi- cal six-layer configuration, then the top- and bottom-mount inductance will be the same. But for a high layer count stackup, planes are best positioned close to the IC, with the decaps mounted on the same side, to reduce induc- tance. It is this configuration that can benefit most from same side placement.