Issue link: https://iconnect007.uberflip.com/i/786015
34 The PCB Design Magazine • February 2017 developed for high-speed PCB design as shown in Figure 1. Over the past year, we have added the following productivity features: • Relative signal propagation with Matched Delay Optimization feature • Termination Planner—IV curves extracted from IBIS models • Heads-up impedance plots created by multiple field solver passes • PDN EMI Plot with FCC, CISPR and VCCI EMC limits • IPC-2581B format, bi-directional interface • Dielectric materials library of 30,700 rigid and flexible materials up to 100GHz. • Capacitor library of 5,650, with Samsung caps added Today's high-speed interfaces simply can- not be modeled using a match-to-length meth- odology—an approach that conventional PCB design tools support. This is because of the tight timing required. A matched length of 2.3 inches for a DDR3/4 data lane, for instance, can produce up to 70ps delta, between signal lay- ers, leaving the timing way outside the required setup and hold times. Consider, for example, a DDR3 interface with eight byte lanes. Each byte lane has data signals, strobe signals, and mask signals. And each grouping of signals has its own set of sig- nals with eight signals in a byte. The timing within each byte lane must be within ~30ps for the highest speed memory. Signals propagate at the speed of light in free space. However, this speed varies dramati- cally depending on the surrounding dielectric materials. Each layer of a multilayer PCB can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The new Matched Delay Optimization feature of the iCD Stackup NEW FUNCTIONALITY IMPROVES DESIGNER'S PRODUCTIVITY Figure 2: Matched delay optimization of each signal layer's relative flight time.