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44 The PCB Design Magazine • March 2017 by Bert Simonovich LAMSIM ENTERPRISES Obsessing over Conductor Surface Roughness: What's the Effect on Dk? BERT'S PRACTICAL DESIGN NOTES You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky moun- tain topology reminds you of conductor surface roughness! Well, call me obsessed, because that's exactly what I thought on my way to Design- Con 2017 in Santa Clara, California. For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness and its effect on insertion loss (IL). I have presented several papers on the subject over the last cou- ple of years. It's one of my pet projects. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittiv- ity and Phase Delay Due to Conductor Surface Roughness." [1] Everyone involved in the design and manufacture of PCBs knows that one of the most important properties of the dielectric ma- terial is the relative permittivity (ε r ), commonly referred to as dielectric constant (D k ). But in re- ality, D k is not constant at all. It varies over fre- quency as you will see later. We often assume the value reported in man- ufacturers' data sheets is the intrinsic property of the material. But in actual fact, it is the ef- fective dielectric constant (D keff ) generated by a specific test method. When you compare sim- ulation against measurements, you will often see a discrepancy in Dkeff and IL, due to the increased phase delay caused by surface rough- ness. This has always bothered me. For a long time, I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent re- search work. Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness pro- file decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective D k and TD. The main focus of my paper was to prove the theory and to show a practical method to model Dkeff and TD due to surface roughness. By ref- erencing Gauss's Law for charged parallel plates, I confirmed mathematically, and through simu- lation, how the dielectric thickness and permit- tivity are interrelated to e-field and capacitance. I also revealed how the 10-point mean (Rz) Figure 1: Rocky mountain high over Colorado, and mulling over conductor surface roughness.